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    Semiconductor memory with vertical memory transistors and method for fabricating it
    11.
    发明申请
    Semiconductor memory with vertical memory transistors and method for fabricating it 有权
    具有垂直存储晶体管的半导体存储器及其制造方法

    公开(公告)号：US20050199942A1

    公开(公告)日：2005-09-15

    申请号：US11073205

    申请日：2005-03-05

    申请人： Franz Hofmann ,  Erhard Landgraf ,  Richard Luyken ,  Thomas Schulz ,  Michael Specht

    发明人： Franz Hofmann ,  Erhard Landgraf ,  Richard Luyken ,  Thomas Schulz ,  Michael Specht

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/792

    CPC分类号： H01L21/28282 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923 ,  H01L29/7926

    摘要： The invention relates to a semiconductor memory having a multiplicity of memory cells and a method for forming the memory cells. The semiconductor memory generally includes a semiconductor layer arranged on a substrate surface that includes a normally positioned step between a deeper region and a higher region. The semiconductor memory further includes doped contact regions, channel regions, a trapping layer arranged on a gate oxide layer, and at least one gate electrode. The method for forming the memory cells includes patterning a semiconductor layer to form a deeper semiconductor region and a higher semiconductor region having a step positioned between the regions. The method further includes forming a first oxide layer and a trapping layer, and then removing portions of the trapping layer and the first oxide layer and applying a second oxide layer at least regions of a doped region, the trapping layer, and the step area, and applying a gate electrode to the second oxide layer and doping, at least in regions, of the deeper semiconductor region and the higher semiconductor region to form a deeper contact region and a higher contact region.

    摘要翻译： 本发明涉及具有多个存储单元的半导体存储器和用于形成存储单元的方法。 半导体存储器通常包括布置在衬底表面上的半导体层，其包括较深区域和较高区域之间的正常定位的台阶。 半导体存储器还包括掺杂接触区域，沟道区域，布置在栅极氧化物层上的俘获层和至少一个栅电极。 形成存储单元的方法包括图案化半导体层以形成较深的半导体区域和具有位于该区域之间的台阶的较高半导体区域。 该方法还包括形成第一氧化物层和俘获层，然后去除俘获层和第一氧化物层的部分，并且至少在掺杂区域，俘获层和台阶区域的区域上施加第二氧化物层， 以及向所述第二氧化物层施加栅电极，并且至少在所述较深半导体区域和所述较高半导体区域的区域中掺杂以形成更深的接触区域和更高的接触区域。

    Fabrication method for memory cell
    12.
    发明申请
    Fabrication method for memory cell 失效
    存储单元制造方法

    公开(公告)号：US20050032311A1

    公开(公告)日：2005-02-10

    申请号：US10899436

    申请日：2004-07-26

    申请人： Franz Hofmann ,  Erhard Landgraf ,  Hannes Luyken

    发明人： Franz Hofmann ,  Erhard Landgraf ,  Hannes Luyken

    IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

    摘要： Method of fabricating a memory cell, in which a storage layer, which is designed for programming by charge carrier trapping, and a gate electrode, which is electrically insulated from a semiconductor material, are fabricated at a top side of a semiconductor body or a semiconductor layer structure above a channel region provided between doped source-drain regions. The method includes the steps of fabricating at least one trench in the top side, providing at least portions of the trench walls which adjoin the source-drain regions to be fabricated with the storage layer, depositing a material provided for the gate electrode into the trench, forming the source-drain regions by covering the gate electrode, removing, on both sides of the trench, the semiconductor material down to an intended depth, and implanting dopant, and applying an insulation layer to the source-drain region, and fabricating an electrical connection for the gate electrode.

    摘要翻译： 制造存储单元的方法，其中设计用于通过电荷载流子捕获进行编程的存储层和与半导体材料电绝缘的栅电极制造在半导体本体或半导体的顶侧 在设置在掺杂源极 - 漏极区之间的沟道区域之上的层结构。 该方法包括以下步骤：在顶侧制造至少一个沟槽，提供沟槽壁的至少部分，其邻接待制造的源极 - 漏极区域与存储层，将为栅电极提供的材料沉积到沟槽 通过覆盖栅极电极形成源极 - 漏极区域，在沟槽的两侧将半导体材料去除到预期深度，并且注入掺杂剂，并且向源极 - 漏极区域施加绝缘层，并且制造 栅电极的电连接。

    Semiconductor memory with vertical memory transistors and method for fabricating it
    14.
    发明授权
    Semiconductor memory with vertical memory transistors and method for fabricating it 有权
    具有垂直存储晶体管的半导体存储器及其制造方法

    公开(公告)号：US07265413B2

    公开(公告)日：2007-09-04

    申请号：US11073205

    申请日：2005-03-05

    申请人： Franz Hofmann ,  Erhard Landgraf ,  Richard Johannes Luyken ,  Thomas Schulz ,  Michael Specht

    发明人： Franz Hofmann ,  Erhard Landgraf ,  Richard Johannes Luyken ,  Thomas Schulz ,  Michael Specht

    IPC分类号： H01L29/792

    CPC分类号： H01L21/28282 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923 ,  H01L29/7926

    摘要： The invention relates to a semiconductor memory having a multiplicity of memory cells and a method for forming the memory cells. The semiconductor memory generally includes a semiconductor layer arranged on a substrate surface that includes a normally positioned step between a deeper region and a higher region. The semiconductor memory further includes doped contact regions, channel regions, a trapping layer arranged on a gate oxide layer, and at least one gate electrode. The method for forming the memory cells includes patterning a semiconductor layer to form a deeper semiconductor region and a higher semiconductor region having a step positioned between the regions. The method further includes forming a first oxide layer and a trapping layer, and then removing portions of the trapping layer and the first oxide layer and applying a second oxide layer at least regions of a doped region, the trapping layer, and the step area, and applying a gate electrode to the second oxide layer and doping, at least in regions, of the deeper semiconductor region and the higher semiconductor region to form a deeper contact region and a higher contact region.

    摘要翻译： 本发明涉及具有多个存储单元的半导体存储器和用于形成存储单元的方法。 半导体存储器通常包括布置在衬底表面上的半导体层，其包括较深区域和较高区域之间的正常定位的台阶。 半导体存储器还包括掺杂接触区域，沟道区域，布置在栅极氧化物层上的俘获层和至少一个栅电极。 形成存储单元的方法包括图案化半导体层以形成较深的半导体区域和具有位于该区域之间的台阶的较高半导体区域。 该方法还包括形成第一氧化物层和俘获层，然后去除俘获层和第一氧化物层的部分，并且至少在掺杂区域，俘获层和台阶区域的区域上施加第二氧化物层， 以及向所述第二氧化物层施加栅电极，并且至少在所述较深半导体区域和所述较高半导体区域的区域中掺杂以形成更深的接触区域和更高的接触区域。

    NROM semiconductor memory device and fabrication method
    17.
    发明申请
    NROM semiconductor memory device and fabrication method 失效
    NROM半导体存储器件及其制造方法

    公开(公告)号：US20060108646A1

    公开(公告)日：2006-05-25

    申请号：US11282904

    申请日：2005-11-18

    申请人： Franz Hofmann ,  Erhard Landgraf ,  Michael Specht

    发明人： Franz Hofmann ,  Erhard Landgraf ,  Michael Specht

    IPC分类号： H01L29/76 ,  H01L21/8234

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/7923

    摘要： This invention relates to a method for producing an NROM semiconductor memory device and a corresponding NROM semiconductor memory device. The inventive production method comprises the following steps: a plurality of spaced-apart U-shaped MOSFETS are provided along rows in a first direction and along gaps in a second direction inside trenches of a semiconductor substrate, said U-shaped MOSFETS comprising a multilayer dielectric, especially an ONO dielectric, for trapping charges; source/drain areas are provided between the U-shaped MOSFETS in intermediate spaces located between the rows that extend parallel to the gaps; insulating trenches are provided in the source/drain areas between the U-shaped MOSFETS of adjacent gaps, down to a certain depth in the semiconductor substrate, said insulating trenches cutting up the source/drain areas into respective bit lines; the insulating trenches are filled with an insulating material; and word lines are provided for connecting respective rows of U-shaped MOSFETS.

    摘要翻译： 本发明涉及一种制造NROM半导体存储器件和相应的NROM半导体存储器件的方法。 本发明的制造方法包括以下步骤：在半导体衬底的沟槽内沿着第一方向并沿着第二方向的间隙沿着行设置多个间隔开的U形MOSFET，所述U形MOSFETS包括多层电介质 ，特别是用于捕获电荷的ONO电介质; 源极/漏极区域设置在位于平行于间隙延伸的行之间的中间空间中的U形MOSFET之间; 绝缘沟槽设置在相邻间隙的U形MOSFET之间的源极/漏极区域中，在半导体衬底内向下到达一定深度，所述绝缘沟槽将源极/漏极区域切割成相应的位线; 绝缘槽填充绝缘材料; 并且提供用于连接各行的U形MOSFET的字线。

    Fin field effect transistor arrangement and method for producing a fin field effect transistor arrangement
    19.
    发明申请
    Fin field effect transistor arrangement and method for producing a fin field effect transistor arrangement 有权
    翅片场效应晶体管布置及其制造方法

    公开(公告)号：US20070096196A1

    公开(公告)日：2007-05-03

    申请号：US11588868

    申请日：2006-10-27

    申请人： Franz Hofmann ,  Erhard Landgraf ,  Richard Luyken

    发明人： Franz Hofmann ,  Erhard Landgraf ,  Richard Luyken

    IPC分类号： H01L29/788 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/00 ,  H01L27/01 ,  H01L31/0392

    CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78636

    摘要： A fin field effect transistor arrangement comprises a substrate and a first fin field effect transistor on and/or in the substrate. The first fin field effect transistor includes a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. A second fin field effect transistor is provided on and/or in the substrate including a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. The second fin field effect transistor is arranged laterally alongside the first fin field effect transistor, wherein a height of the fin of the first fin field effect transistor is greater than a height of the fin of the second fin field effect transistor.

    摘要翻译： 鳍状场效应晶体管布置包括衬底和衬底上和/或衬底中的第一鳍状场效应晶体管。 第一鳍状场效应晶体管包括鳍状物，其中在第一源极/漏极区域和第二源极/漏极区域之间形成沟道区域，并且在其上形成栅极区域。 第二鳍状场效应晶体管设置在衬底上和/或衬底中，包括在第一源极/漏极区域和第二源极/漏极区域之间形成沟道区域的鳍片，并且在其上形成栅极区域。 第二鳍状场效应晶体管沿第一鳍状场效应晶体管横向布置，其中第一鳍状场效应晶体管的鳍的高度大于第二鳍状场效应晶体管的鳍的高度。