公开(公告)号：US20170046395A1

公开(公告)日：2017-02-16

申请号：US15305960

申请日：2014-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Sheng Li ,  Kevin T. Lim ,  Dejan S. Milojicic ,  Paolo Faraboschi

IPC: G06F17/30 ,  G06F3/06

CPC classification number: G06F17/30495 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0673 ,  G06F17/30097 ,  G06F17/3033 ,  G06F17/30584

Abstract: A bit vector for a Bloom filter is determined by performing one or more hash function operations on a set of ternary content addressable memory (TCAM) words. A TCAM array is partitioned into a first portion to store the bit vector for the Bloom filter and a second portion to store the set of TCAM words. The TCAM array can be searched using a search word by performing the one or more hash function operations on the search word to generate a hashed search word and determining whether bits at specified positions of the hashed search word match bits at corresponding positions of the bit vector stored in the first portion of the TCAM array before searching the second portion of the TCAM array with the search word.

Abstract translation: 通过对一组三元内容可寻址存储器（TCAM）字进行一个或多个散列函数操作来确定布隆过滤器的位向量。 将TCAM阵列划分为第一部分以存储布隆过滤器的位向量，以及存储该组TCAM字的第二部分。 可以使用搜索词搜索TCAM阵列，通过对搜索词执行一个或多个哈希函数操作来产生散列搜索词，并确定散列搜索词的指定位置的比特是否与比特向量的相应位置的比特匹配 存储在TCAM阵列的第一部分中，然后用搜索词搜索TCAM阵列的第二部分。

公开(公告)号：US20240020155A1

公开(公告)日：2024-01-18

申请号：US18476690

申请日：2023-09-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Dejan S. Milojicic ,  Kimberly Keeton ,  Paolo Faraboschi ,  Cullen E. Bash

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06F9/505 ,  G06F9/5044 ,  G06F9/5005 ,  G06F9/5055

Abstract: Systems and methods are provided for incorporating an optimized dispatcher with an FaaS infrastructure to permit and restrict access to resources. For example, the dispatcher may assign requests to “warm” resources and initiate a fault process if the resource is overloaded or a cache-miss is identified (e.g., by restarting or rebooting the resource). The warm instances or accelerators associated with the allocation size that are identified may be commensurate to the demand and help dynamically route requests to faster accelerators.

公开(公告)号：US11294763B2

公开(公告)日：2022-04-05

申请号：US16115100

申请日：2018-08-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Paul Strachan ,  Catherine Graves ,  Dejan S. Milojicic ,  Paolo Faraboschi ,  Martin Foltin ,  Sergey Serebryakov

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52

Abstract: A computer system includes multiple memory array components that include respective analog memory arrays which are sequenced to implement a multi-layer process. An error array data structure is obtained for at least a first memory array component, and from which a determination is made as to whether individual nodes (or cells) of the error array data structure are significant. A determination can be made as to any remedial operations that can be performed to mitigate errors of significance.

公开(公告)号：US10769017B2

公开(公告)日：2020-09-08

申请号：US15960302

申请日：2018-04-23

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Cong Xu ,  Itir Akgun ,  Paolo Faraboschi

IPC: G06F11/00 ,  G06F11/14 ,  H04L29/08

Abstract: In some examples, with respect to adaptive multi-level checkpointing, a transfer parameter associated with transfer of checkpoint data from a node-local storage to a parallel file system may be ascertained for the checkpoint data stored in the node-local storage. The transfer parameter may be compared to a specified transfer parameter threshold. A determination may be made, based on the comparison of the transfer parameter to the specified transfer parameter threshold, as to whether to transfer the checkpoint data from the node-local storage to the parallel file system.

公开(公告)号：US10756756B2

公开(公告)日：2020-08-25

申请号：US16131722

申请日：2018-09-14

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Anirban Nag ,  Naveen Muralimanohar ,  Paolo Faraboschi

IPC: H03M7/30 ,  H03M7/24

Abstract: Computer-implemented methods, systems, and devices to perform lossless compression of floating point format time-series data are disclosed. A first data value may be obtained in floating point format representative of an initial time-series parameter. For example, an output checkpoint of a computer simulation of a real-world event such as weather prediction or nuclear reaction simulation. A first predicted value may be determined representing the parameter at a first checkpoint time. A second data value may be obtained from the simulation. A prediction error may be calculated. Another predicted value may be generated for a next point in time and may be adjusted by the previously determined prediction error (e.g., to increase accuracy of the subsequent prediction). When a third data value is obtained, the adjusted prediction value may be used to generate a difference (e.g., XOR) for storing in a compressed data store to represent the third data value.

公开(公告)号：US10725940B2

公开(公告)日：2020-07-28

申请号：US16167494

申请日：2018-10-22

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Qiong Cai ,  Paolo Faraboschi ,  Cong Xu ,  Ping Chi ,  Sai Rahul Chalamalasetti ,  Andrew C. Walton

IPC: G06F13/16 ,  G06F15/76 ,  G06F9/38

Abstract: Techniques for reallocating a memory pending queue based on stalls are provided. In one aspect, it may be determined at a memory stop of a memory fabric that at least one class of memory access is stalled. It may also be determined at the memory stop of the memory fabric that there is at least one class of memory access that is not stalled. At least a portion of a memory pending queue may be reallocated from the class of memory access that is not stalled to the class of memory access that is stalled.

公开(公告)号：US10324644B2

公开(公告)日：2019-06-18

申请号：US15476185

申请日：2017-03-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Kaisheng Ma ,  Qiong Cai ,  Cong Xu ,  Paolo Faraboschi

IPC: G06F12/00 ,  G06F3/06 ,  G06F15/78 ,  G06F9/48 ,  G06F9/50

Abstract: Examples described herein include receiving an operation pipeline for a computing system and building a graph that comprises a model for a number of potential memory side accelerator thread assignments to carry out the operation pipeline. The computing system may comprise at least two memories and a number of memory side accelerators. Each model may comprise a number of steps and at least one step out of the number of steps in each model may comprise a function performed at one memory side accelerator out of the number of memory side accelerators. Examples described herein also include determining a cost of at least one model.

公开(公告)号：US10254988B2

公开(公告)日：2019-04-09

申请号：US15500754

申请日：2015-03-12

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Rajeev Balasubramonian ,  Gregg B. Lesartre ,  Robert Schreiber ,  Jishen Zhao ,  Naveen Muralimanohar ,  Paolo Faraboschi

IPC: G06F3/06 ,  G06F11/10 ,  G06F12/02 ,  G11C7/10 ,  G11C7/22 ,  G06F12/14

Abstract: Techniques for memory device writes based on mapping are provided. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise multiple memory devices. The block of data may be written to a number of memory devices determined by the size of the block of data. A memory device mapping for the line may be retrieved. The mapping may determine the order in which the block of data is written to the memory devices within the rank. The block of data may be written to the memory devices based on the mapping.

公开(公告)号：US10241911B2

公开(公告)日：2019-03-26

申请号：US15246136

申请日：2016-08-24

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gabriel Parmer ,  Paolo Faraboschi ,  Dejan S Milojicic

IPC: G06F12/0808 ,  G06F12/0831 ,  G06F12/0811

Abstract: Examples described herein relate to caching in a system with multiple nodes sharing a globally addressable memory. The globally addressable memory includes multiple windows that each include multiple chunks. Each node of a set of the nodes includes a cache that is associated with one of the windows. One of the nodes includes write access to one of the chunks of the window. The other nodes include read access to the chunk. The node with write access further includes a copy of the chunk in its cache and modifies multiple lines of the chunk copy. After a first line of the chunk copy is modified, a notification is sent to the other nodes that the chunk should be marked dirty. After multiple lines are modified, an invalidation message is sent for each of the modified lines of the set of the nodes.

公开(公告)号：US20190056872A1

公开(公告)日：2019-02-21

申请号：US16167494

申请日：2018-10-22

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Qiong Cai ,  Paolo Faraboschi ,  Cong Xu ,  Ping Ping ,  Sai Rahul Chalamalasetti ,  Andrew C. Walton

IPC: G06F3/06 ,  G06F13/16 ,  G06F9/38

Abstract: Techniques for reallocating a memory pending queue based on stalls are provided. In one aspect, it may be determined at a memory stop of a memory fabric that at least one class of memory access is stalled. It may also be determined at the memory stop of the memory fabric that there is at least one class of memory access that is not stalled. At least a portion of a memory pending queue may be reallocated from the class of memory access that is not stalled to the class of memory access that is stalled.