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    LIST DECODE CIRCUITS
    11.
    发明申请
    LIST DECODE CIRCUITS 审中-公开

    公开(公告)号：US20180219560A1

    公开(公告)日：2018-08-02

    申请号：US15417431

    申请日：2017-01-27

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Chris Michael Brueggen ,  Ron M. Roth

    IPC: H03M13/15 ,  H03M13/00

    CPC classification number: H03M13/153 ,  H03M13/1515 ,  H03M13/1565 ,  H03M13/158 ,  H03M13/6502

    Abstract: Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of list decode circuits. In accordance with some examples disclosed herein, a device may include a first and second polynomial evaluation circuit, a field division circuit, a discrepancy filter, and an enhanced error locator polynomial (ELP) circuit. The first and second polynomial evaluation circuits may respectively evaluate a first and second polynomial output from a Berlekamp-Massey algorithm over a plurality of values in a finite field. The field division circuit may divide the outputs from the evaluations to generate a plurality of speculative discrepancy values for an additional iteration of the Berlekamp-Massey algorithm. The discrepancy filter circuit may filter the speculative discrepancy values down to a list of potentially valid discrepancy values that may be used by the enhanced ELP circuit to generate an enhanced ELP.

    BIT-FLIP CODING
    12.
    发明申请
    BIT-FLIP CODING 审中-公开
    位转码

    公开(公告)号：US20160352358A1

    公开(公告)日：2016-12-01

    申请号：US15112013

    申请日：2014-01-24

    Applicant: HEWLETT-PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Erik Ordentlich ,  Ron M. Roth

    IPC: H03M13/15 ,  G11C29/52 ,  G06F11/10

    CPC classification number: H03M13/1575 ,  G06F11/1068 ,  G11C29/52 ,  H03M13/2921 ,  H03M13/47 ,  H03M13/51

    Abstract: Bit-flip coding uses a bit-flip encoder to flip bits in a redundancy-intersecting vector of a binary array having n rows and n columns until Hamming weights of the binary array are within a predetermined range Δ of n divided by two. Information bits of an input data word to the bit-flip coding apparatus are stored in locations within the binary array that are not occupied by n redundancy bits of a redundancy vector.

    Abstract translation: 位翻转编码使用位触发编码器翻转具有n行和n列的二进制数组的冗余相交向量中的位，直到二进制数组的汉明权重在n的预定范围Δ除以2。 位数翻转编码装置的输入数据字的信息位被存储在二进制数组内不被冗余向量的n个冗余比特占用的位置中。

    Error-detection schemes for analog content-addressable memories
    13.
    发明授权
    Error-detection schemes for analog content-addressable memories 有权

    公开(公告)号：US11978523B1

    公开(公告)日：2024-05-07

    申请号：US17983050

    申请日：2022-11-08

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Ron M. Roth ,  Catherine Graves

    IPC: G11C29/10 ,  G11C15/04 ,  G11C27/00

    CPC classification number: G11C29/10 ,  G11C15/046 ,  G11C27/005

    Abstract: Examples of the presently disclosed technology provide new circuits for detecting errors in aCAMs with improved efficiency. Specifically designed around the structure and operation of aCAM arrays, these circuits include counter sub-circuits electrically connected to match lines of aCAM rows such that the counter sub-circuits receive match-related signals output from aCAM rows. The value stored by a counter sub-circuit may change in response to receiving a match signal, and may remain the same in response to receiving a mismatch signal. As will be described in greater detail below, the stored value of the counter sub-circuit may be used to detect/identify an error in its associated aCAM row after a set of (specially-computed) error-detection input vectors are sequentially applied to the circuit.

    Storing run-length limited two-dimensional encoded bit patterns in memory arrays
    15.
    发明授权
    Storing run-length limited two-dimensional encoded bit patterns in memory arrays 有权

    公开(公告)号：US10102205B2

    公开(公告)日：2018-10-16

    申请号：US15111703

    申请日：2014-01-30

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Erik Ordentlich ,  Ron M. Roth

    IPC: G06F17/30 ,  G11C13/00 ,  G06F3/06

    Abstract: In one implementation, a data storage system includes a memory array having memory devices in a crossbar configuration, and a memory controller for controlling data storage in the memory array. The memory controller includes an encoder to generate a 2-dimensional encoded bit pattern that encodes an input data. Each run-length of 0's and each run-length of 1's in each row or each column of the encoded bit pattern are at least of a predefined lower limit. The predefined lower limit is at least two. The memory controller includes a write controller to write the encoded bit pattern into the memory devices of the memory array, such that a number of consecutive memory devices in each row or each column of the memory array having a same state is based on the encoded bit pattern.

    CONSTANT HAMMING WEIGHT CODING
    17.
    发明申请
    CONSTANT HAMMING WEIGHT CODING 有权
    恒定重量编码

    公开(公告)号：US20160352359A1

    公开(公告)日：2016-12-01

    申请号：US15113903

    申请日：2014-01-31

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Erik Ordentlich ,  Ron M. Roth

    IPC: H03M13/15 ,  H03M13/51

    CPC classification number: H03M13/1575 ,  H03M13/155 ,  H03M13/51

    Abstract: Encoding or decoding can operate a processing system to apply one or more recursive relations to a known parameter associated with a length m and a Hamming weight l to produce a computed parameter associated with length m−1. An encoding process can thus assign values to bits of a code based on comparison of the data value being encoded and the computed parameter. A decoding process can use the computed parameters in a calculation of a decoded data value.

    Abstract translation: 编码或解码可以操作处理系统以将一个或多个递归关系应用于与长度m和汉明权重1相关联的已知参数，以产生与长度m-1相关联的计算参数。 因此，编码处理可以基于正在编码的数据值与所计算的参数的比较来将值分配给代码的位。 在解码数据值的计算中，解码处理可以使用计算出的参数。

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