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公开(公告)号：US12106805B2
公开(公告)日：2024-10-01
申请号：US17872882
申请日：2022-07-25
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Tobias Frederic Ziegler , Ron M. Roth , Giacomo Pedretti , Luca Buonanno , Pedro Henrique Rocha Bruel , Catherine Graves
IPC: G11C15/04 , G11C16/10 , G11C16/12 , H03K19/017
CPC classification number: G11C15/04 , G11C16/102 , G11C16/12 , H03K19/01742
Abstract: Examples increase precision for aCAMs by converting an input signal (x) received by a circuit into a first analog voltage signal (V(xMSB)) representing the most significant bits of the input signal (x) and a second analog voltage signal (V(xLSB)) representing the least significant bits of the input signal (x). By dividing the input signal (x) bit-wise into the first analog voltage signal (V(xMSB)) and the second analog voltage signal (V(xLSB)), the circuit can utilize aCAM sub-circuits implementing a combination of Boolean operations to search the input signal (x) against 22*M programmable levels, where “M” represents the number of programmable bits for each aCAM sub-circuit. Thus, using similar circuit hardware, example circuits square the number of programmable levels of conventional aCAMs (which generally only have 2M programmable levels). Accordingly, examples provide new aCAMs that can carry out more complex computations than conventional aCAMs of comparable cost, size, and power consumption.
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公开(公告)号：US10320420B2
公开(公告)日：2019-06-11
申请号：US15112013
申请日：2014-01-24
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Erik Ordentlich , Ron M. Roth
Abstract: Bit-flip coding uses a bit-flip encoder to flip bits in a redundancy-intersecting vector of a binary array having n rows and n columns until Hamming weights of the binary array are within a predetermined range Δ of n divided by two. Information bits of an input data word to the bit-flip coding apparatus are stored in locations within the binary array that are not occupied by n redundancy bits of a redundancy vector.
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公开(公告)号：US09952796B2
公开(公告)日：2018-04-24
申请号：US15113890
申请日：2014-01-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Erik Ordentlich , Ron M. Roth
CPC classification number: G06F3/064 , G06F3/0619 , G06F3/0644 , G06F3/0679 , G06F11/1068 , G06F12/0238 , G06F12/0607 , G11C29/52 , G11C2029/0411
Abstract: Methods and systems for storing data in memory arrays are described. In one implementation, input bits are encoded into an intermediate binary array having multiple sub-arrays iteratively appended row-wise to the intermediate binary array. First sub-array is generated based on the input bits such that each row of the first sub-array has a number of 1's equal to a fraction of number of columns in the first sub-array, and based on a column balance coding such that the columns of the first sub-array have an equal number of 1's. At least one subsequent sub-array is generated based on a set of bits obtained from balancing termination indices for a previous sub-array and from diagonal bits of the intermediate binary array that are a part of the previous appended sub-array. The intermediate binary array is transformed to an encoded bit pattern. The encoded bit pattern is stored in the memory array.
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公开(公告)号：US20160350000A1
公开(公告)日：2016-12-01
申请号：US15113890
申请日：2014-01-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Erik Ordentlich , Ron M. Roth
CPC classification number: G06F3/064 , G06F3/0619 , G06F3/0644 , G06F3/0679 , G06F11/1068 , G06F12/0238 , G06F12/0607 , G11C29/52 , G11C2029/0411
Abstract: Methods and systems for storing data in memory arrays are described. In one implementation, input bits are encoded into an intermediate binary array having multiple sub-arrays iteratively appended row-wise to the intermediate binary array. First sub-array is generated based on the input bits such that each row of the first sub-array has a number of 1's equal to a fraction of number of columns in the first sub-array, and based on a column balance coding such that the columns of the first sub-array have an equal number of 1's. At least one subsequent sub-array is generated based on a set of bits obtained from balancing termination indices for a previous sub-array and from diagonal bits of the intermediate binary array that are a part of the previous appended sub-array. The intermediate binary array is transformed to an encoded bit pattern. The encoded bit pattern is stored in the memory array.
Abstract translation: 描述了将数据存储在存储器阵列中的方法和系统。 在一个实现中，输入比特被编码成具有逐行地附加到中间二进制数组的多个子阵列的中间二进制数组。 基于输入比特生成第一子阵列，使得第一子阵列的每行的数目等于第一子阵列中的列数量的一部分，并且基于列平衡编码，使得 第一个子阵列的列具有相等数量的1。 基于从先前子阵列的平衡终止索引和作为前一个附加子阵列的一部分的中间二进制数组的对角位获得的一组比特来生成至少一个后续子阵列。 将中间二进制数组变换为编码位模式。 编码位模式存储在存储器阵列中。
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公开(公告)号：US20240170082A1
公开(公告)日：2024-05-23
申请号：US17983050
申请日：2022-11-08
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Ron M. Roth , Catherine Graves
CPC classification number: G11C29/10 , G11C15/046 , G11C27/005
Abstract: Examples of the presently disclosed technology provide new circuits for detecting errors in aCAMs with improved efficiency. Specifically designed around the structure and operation of aCAM arrays, these circuits include counter sub-circuits electrically connected to match lines of aCAM rows such that the counter sub-circuits receive match-related signals output from aCAM rows. The value stored by a counter sub-circuit may change in response to receiving a match signal, and may remain the same in response to receiving a mismatch signal. As will be described in greater detail below, the stored value of the counter sub-circuit may be used to detect/identify an error in its associated aCAM row after a set of (specially-computed) error-detection input vectors are sequentially applied to the circuit.
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Patent Agency Ranking
公开(公告)号：US11061766B2
公开(公告)日：2021-07-13
申请号：US16712358
申请日：2019-12-12
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Ron M. Roth , Richard H. Henze
Abstract: Examples disclosed herein relate to a fault-tolerant dot product engine. The fault-tolerant dot product engine has a crossbar array having a number l of row lines and a number n of column lines intersecting the row lines to form l×n memory locations, with each memory location having a programmable memristive element and defining a matrix value. A number l of digital-to-analog converters are coupled to the row lines of the crossbar array to receive an input signal and a number n of analog-to-digital converters are coupled to the column lines of the crossbar array to generate an output signal. The output signal is a dot product of the input signal and the matrix values in the crossbar array, wherein a number m
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公开(公告)号：US10367529B2
公开(公告)日：2019-07-30
申请号：US15417431
申请日：2017-01-27
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Chris Michael Brueggen , Ron M. Roth
Abstract: Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of list decode circuits. In accordance with some examples disclosed herein, a device may include a first and second polynomial evaluation circuit, a field division circuit, a discrepancy filter, and an enhanced error locator polynomial (ELP) circuit. The first and second polynomial evaluation circuits may respectively evaluate a first and second polynomial output from a Berlekamp-Massey algorithm over a plurality of values in a finite field. The field division circuit may divide the outputs from the evaluations to generate a plurality of speculative discrepancy values for an additional iteration of the Berlekamp-Massey algorithm. The discrepancy filter circuit may filter the speculative discrepancy values down to a list of potentially valid discrepancy values that may be used by the enhanced ELP circuit to generate an enhanced ELP.
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公开(公告)号：US20160329097A1
公开(公告)日：2016-11-10
申请号：US15111703
申请日：2014-01-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Erik Ordentlich , Ron M. Roth
CPC classification number: G06F17/30 , G06F3/0604 , G06F3/0638 , G06F3/0679 , G11C13/0007 , G11C13/004 , G11C13/0069
Abstract: Methods and systems for storing data in memory arrays are described. In one implementation, a data storage system includes a memory array having memory devices in a crossbar configuration, and a memory controller for controlling data storage in the memory array. The memory controller includes an encoder to generate a 2-dimensional encoded bit pattern that encodes the input data. Each run-length of 0's and each run-length of 1's in each row or each column of the encoded bit pattern are at least of a predefined lower limit. The predefined lower limit is at least two. The memory controller includes a write controller to write the encoded bit pattern into the memory devices of the memory array, such that a number of consecutive memory devices in each row or each column of the memory array having a same state is based on the encoded bit pattern.
Abstract translation: 描述了将数据存储在存储器阵列中的方法和系统。 在一个实现中，数据存储系统包括具有交叉开关配置的存储器件的存储器阵列和用于控制存储器阵列中的数据存储的存储器控制器。 存储器控制器包括编码器，用于产生对输入数据进行编码的2维编码位模式。 编码比特模式的每行或每列的每个游程长度为0，每个游程长度为1，至少为预定义的下限。 预定义的下限至少为2。 存储器控制器包括写控制器，用于将编码位模式写入存储器阵列的存储器件，使得存储器阵列的每行或每列中具有相同状态的多个连续存储器件基于编码位 模式。
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公开(公告)号：US20240249787A1
公开(公告)日：2024-07-25
申请号：US18347318
申请日：2023-07-05
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： GIACOMO PEDRETTI , Ron M. Roth
IPC: G11C27/00
CPC classification number: G11C27/005
Abstract: Examples of the presently disclosed technology provide “tree-CAMs” specially constructed to implement decision trees more efficiently—namely with less hardware (i.e., fewer memristors and transistors), less power consumption, and less memristor programming time than existing aCAMs used to implement decision trees. A tree-CAM realizes these optimizations by leveraging a shared comparison sub-circuit that stores a threshold shared among evaluable conditions for multiple root-to-leaf-paths of a decision tree. The threshold may be evaluated against a common feature of a feature vector. The shared comparison sub-circuit may comprise just a single memristor programmed to store the threshold. Accordingly, the tree-CAM can represent/implement evaluable conditions (sharing a common threshold and evaluated against a common feature) across multiple root-to-leaf paths of a decision tree using just a single memristor—thus reducing the number of memristors required to implement the decision tree.
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公开(公告)号：US10545821B2
公开(公告)日：2020-01-28
申请号：US15664874
申请日：2017-07-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Ron M. Roth , Richard H. Henze
Abstract: Examples disclosed herein relate to a fault-tolerant dot product engine. The fault-tolerant dot product engine has a crossbar array having a number l of row lines and a number n of column lines intersecting the row lines to form l×n memory locations, with each memory location having a programmable memristive element and defining a matrix value. A number l of digital-to-analog converters are coupled to the row lines of the crossbar array to receive an input signal and a number n of analog-to-digital converters are coupled to the column lines of the crossbar array to generate an output signal. The output signal is a dot product of the input signal and the matrix values in the crossbar array, wherein a number m
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