System and method for an asynchronous processor with a hierarchical token system
    12.
    发明授权
    System and method for an asynchronous processor with a hierarchical token system 有权
    具有分层令牌系统的异步处理器的系统和方法

    公开(公告)号:US09495316B2

    公开(公告)日:2016-11-15

    申请号:US14480330

    申请日:2014-09-08

    CPC classification number: G06F13/385

    Abstract: Embodiments are provided for an asynchronous processor with a Hierarchical Token System. The asynchronous processor includes a set of primary processing units configured to gate and pass a set of tokens in a predefined order of a primary token system. The asynchronous processor further includes a set of secondary units configured to gate and pass a second set of tokens in a second predefined order of a secondary token system. The set of tokens of the primary token system includes a token consumed in the set of primary processing units and designated for triggering the secondary token system in the set of secondary units.

    Abstract translation: 为具有分层令牌系统的异步处理器提供实施例。 异步处理器包括一组主处理单元,其被配置为按照主要令牌系统的预定义顺序来选择和传递一组令牌。 异步处理器还包括一组辅助单元,其被配置为以辅助令牌系统的第二预定义顺序选通和传递第二组令牌。 主令牌系统的令牌集合包括在主处理单元组中消耗的令牌,并被指定用于触发该次要单元组中的辅助令牌系统。

    REFERENCE SIGNAL ASSIGNMENT
    13.
    发明申请

    公开(公告)号:US20250088323A1

    公开(公告)日:2025-03-13

    申请号:US18956809

    申请日:2024-11-22

    Abstract: Aspects of the present disclosure relate to a reference signal assignment, in which reference signals for a first apparatus may be assigned based on second channel estimates for one or more second apparatus having a same location and network resource configuration as the first apparatus.

    SYSTEM AND METHOD FOR JOINT SENSING OF INTERFERENCE IN A WIRELESS NETWORK

    公开(公告)号:US20250016595A1

    公开(公告)日:2025-01-09

    申请号:US18883475

    申请日:2024-09-12

    Abstract: Systems and methods of reporting wireless channel state information are provided. With the provided system and method, in a situation where there are multiple UEs which are close to each other, such that channel conditions may be similar for the multiple UEs, one of the UEs is configured to report interference information on a time pattern that has at least two measurement time durations for which interference is to be measured, for example, only for a subset of N consecutive measurement time durations. Other UEs may be configured to report interference information for different time patterns, for example different subsets of the N time slots.

    INTERFACING WITH CODED INFERENCE NETWORKS
    15.
    发明公开

    公开(公告)号:US20240320511A1

    公开(公告)日:2024-09-26

    申请号:US18651215

    申请日:2024-04-30

    CPC classification number: G06N3/098

    Abstract: Some embodiments of the present disclosure relate to inferencing using a trained deep neural network. Inferencing may, reasonably, be expected to be a mainstream application of 6G wireless networks. Agile, robust and accurate inferencing is important for the success of AI applications. Aspects of the present application relate to introducing coding theory into inferencing in a distributed manner. It may be shown that redundant wireless bandwidths and edge units help to ensure agility, robustness and accuracy in coded inferencing networks.

    Broadcast Signal Sending Method, Broadcast Signal Receiving Method, Network Device, and Terminal Device

    公开(公告)号:US20220248372A1

    公开(公告)日:2022-08-04

    申请号:US17561357

    申请日:2021-12-23

    Abstract: A broadcast signaling method performed by a network device having a protocol stack of with first and second protocol layers where the second protocol layer is below the first protocol layer, the method including generating, by the network device, first information at the first protocol layer, generating, by the network device, second information at the second protocol layer, where the second information is used to determine a time-frequency resource corresponding to one or more synchronization signal blocks (SSBs), processing, by the network device, the first information and the second information at the second protocol layer, and sending, by the network device to a terminal device by using a physical broadcast channel (PBCH) in the one or more SSBs, data obtained after second protocol layer processing.

    Method to generate ordered sequence for polar codes

    公开(公告)号:US10985871B2

    公开(公告)日:2021-04-20

    申请号:US15875766

    申请日:2018-01-19

    Abstract: A number K of N sub-channels that are defined by a code and that have associated reliabilities for input bits at N input bit positions, are to be selected to carry bits that are to be encoded. A localization area that includes multiple sub-channels and is located below fewer than K of the N sub-channels in a partial order of the N sub-channels is determined based on one or more coding parameters. The fewer than K sub-channels of the N sub-channels above the localization area in the partial order are selected, and a number of sub-channels from those in the localization area are also selected. The selected fewer than K sub-channels and the number of sub-channels selected from those in the localization area together include K sub-channels to carry the bits that are to be encoded.

    Method and apparatus for sending modulation and coding scheme (MCS)

    公开(公告)号:US10931397B2

    公开(公告)日:2021-02-23

    申请号:US16695216

    申请日:2019-11-26

    Abstract: This application provides a method for communicating a modulation and coding scheme (MCS). A terminal device obtains a modulation order, a code rate, or a spectral efficiency, determines an index of a reference MCS from a mapping table based on the obtained modulation order, code rate, or spectral efficiency, and reports the index of the reference MCS to a network device. The mapping table includes one or more mapping relationships between an MCS index and a modulation order, a code rate, or a spectral efficiency. The terminal device may process uplink or downlink data based on the determined MCS, thereby improving data transmission reliability.

    System and method for an asynchronous processor with pepelined arithmetic and logic unit

    公开(公告)号:US10318305B2

    公开(公告)日:2019-06-11

    申请号:US14477536

    申请日:2014-09-04

    Abstract: Embodiments are provided for an asynchronous processor with pipelined arithmetic and logic unit. The asynchronous processor includes a non-transitory memory for storing instructions and a plurality of instruction execution units (XUs) arranged in a ring architecture for passing tokens. Each one of the XUs comprises a logic circuit configured to fetch a first instruction from the non-transitory memory, and execute the first instruction. The logic circuit is also configured to fetch a second instruction from the non-transitory memory, and execute the second instruction, regardless whether the one of the XUs holds a token for writing the first instruction. The logic circuit is further configured to write the first instruction to the non-transitory memory after fetching the second instruction.

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