公开(公告)号：US20070242741A1

公开(公告)日：2007-10-18

申请号：US11405997

申请日：2006-04-18

申请人： Juan Carballo ,  Hayden Cranford ,  Gareth Nicholls ,  Vernon Norman ,  Martin Schmatz

发明人： Juan Carballo ,  Hayden Cranford ,  Gareth Nicholls ,  Vernon Norman ,  Martin Schmatz

IPC分类号： H03H7/30

CPC分类号： H04L25/03063

摘要： Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.

摘要翻译： 公开了一种在接收机中利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的接收器电路，方法和设计架构，并且降低了误码率（BER ）。 集成接收机与决策反馈均衡器以及适当的（CDR）环路相位检测器相结合，以保持每位需求的单个采样。 输入电压被转换为电流并连接到电流求和节点。 由先前检测到的位及其各自的反馈系数的值确定的加权电流也连接到该节点。 另外，总和电流被积分并转换成电压。 采样器用于基于所得到的电压进行位决定。 采样后，积分器在分析下一位之前被复位。 通过使用在数据锁存器前面的积分来最大化锁存器的灵敏度来实现必要的放大。

公开(公告)号：US20060029177A1

公开(公告)日：2006-02-09

申请号：US11249851

申请日：2005-10-13

申请人： Hayden Cranford ,  Vernon Norman ,  Martin Schmatz

发明人： Hayden Cranford ,  Vernon Norman ,  Martin Schmatz

IPC分类号： H03D3/24

CPC分类号： H03L7/08 ,  H03L7/095 ,  H03L7/0995 ,  H03L7/10 ,  H04L7/0337 ,  H04L2027/0067

摘要： A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.

公开(公告)号：US20070096720A1

公开(公告)日：2007-05-03

申请号：US11262101

申请日：2005-10-28

申请人： Steven Clements ,  William Cornwell ,  Carrie Cox ,  Hayden Cranford ,  Vernon Norman

发明人： Steven Clements ,  William Cornwell ,  Carrie Cox ,  Hayden Cranford ,  Vernon Norman

IPC分类号： G01R31/28

CPC分类号： G01R35/007 ,  Y10T29/49004 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49174

摘要： Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

摘要翻译： 将被测器件（DUT）的输出阻抗基本上精确地校准到允许阻抗的预定范围内。 DUT是源极串行端接（SST）串行链路发射机的一部分，其中当并联支路的特定晶体管导通时，并联晶体管的两个分支都提供阻抗值。 将阻抗值加到串联电阻器上以提供输出阻抗。 DUT由与电阻器串联的并行晶体管的一个分支组成。 将DUT的输出阻抗与参考电阻的电阻进行比较，并且比较器根据输出阻抗是否落在参考电阻的预设百分比方差内提供控制信号。 控制信号由FSM（有限状态机）进行处理，FSM单独打开或关闭并联支路内的晶体管，直到DUT阻抗值落在所需范围内。

公开(公告)号：US20060045224A1

公开(公告)日：2006-03-02

申请号：US10915790

申请日：2004-08-11

申请人： Hayden Cranford ,  Gareth Nicholls ,  Vernon Norman ,  Martin Schmatz ,  Karl Selander ,  Michael Sorna

发明人： Hayden Cranford ,  Gareth Nicholls ,  Vernon Norman ,  Martin Schmatz ,  Karl Selander ,  Michael Sorna

IPC分类号： H04L7/00

CPC分类号： H04L7/0337 ,  H03L7/091 ,  H03L2207/50

摘要： Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by slowing the clock rate with respect to the sampling clock. For instance, the slower clock rate may be implemented by dividing the frequency of the sampling clock by a number such as 128, slowing a sampling clock frequency designed to handle multiple gigabits per second (Gbps) to a frequency of less than one kilohertz (Khz). In addition to the reduced power consumption realized by operating at a lower frequency, the slower clock rate allows components of the CDR loop circuitry to operate a lower operating voltage reducing power consumption by the CDR loop even more.

摘要翻译： 公开了基于从输入数据信号导出的数据样本子集或值的确定时钟和数据恢复（CDR）循环的采样时钟的相位调整的方法和装置。 具体地，实施例通过相对于采样时钟减慢时钟速率来扩展CDR环路。 例如，较慢的时钟速率可以通过将采样时钟的频率除以诸如128的数字来实现，将被设计为处理多吉比特每秒（Gbps）的采样时钟频率减慢到小于1千赫兹的频率（Khz ）。 除了通过以较低频率操作实现的降低的功耗之外，较慢的时钟速率允许CDR环路电路的组件操作较低的工作电压，从而降低CDR环路的功耗。

公开(公告)号：US20050076279A1

公开(公告)日：2005-04-07

申请号：US10680679

申请日：2003-10-07

申请人： Hayden Cranford ,  Vernon Norman ,  Martin Schmatz

发明人： Hayden Cranford ,  Vernon Norman ,  Martin Schmatz

IPC分类号： G01R31/317 ,  G06K5/04 ,  G01R31/28

CPC分类号： G01R31/31901 ,  G01R31/31707

摘要： A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.

摘要翻译： 公开了一种用于测试高速电路的方法和系统。 该方法和系统包括使用常规测试仪获得高速电路的高速统计特征。 该方法和系统还包括将高速电路的高速统计签名与预期签名进行比较。 因此，可以确定高速电路是否在期望的参数内起作用。

公开(公告)号：US20070047589A1

公开(公告)日：2007-03-01

申请号：US11211125

申请日：2005-08-24

申请人： Bobak Modaress-Razavi ,  Vernon Norman

发明人： Bobak Modaress-Razavi ,  Vernon Norman

IPC分类号： H04J3/06 ,  H04J3/04

CPC分类号： H03M9/00 ,  H04J3/0685

摘要： A serializer/deserializer (SERDES) receiver circuit designed to support multiple serial data rates (full, half, and quarter rates) based on user selection, while requiring substantially minimal amounts of additional logic and complexity within the core logic functions and analog circuits of a full rate SERDES. Over-sampled data from the analog block is provided to support each of the different rates, and the data is stored in three preliminary rate registers, one for full rate, one for half rate and one for quarter rate. In full rate mode, all samples coming from the analog circuits are utilized. In half rate and quarter rate modes, one out of every two samples and one out of every four samples is utilized, respectively. The selected samples are converted to parallel data by core logic functions, which are provided a single clock signal corresponding to the particular mode of operation.

摘要翻译： 串行器/解串器（SERDES）接收器电路，其设计用于基于用户选择来支持多个串行数据速率（全，半和四分之一速率），同时在核心逻辑功能和模拟电路中需要基本上最小量的附加逻辑和复杂性 全速SERDES。 提供来自模拟块的过采样数据以支持每个不同的速率，并且数据存储在三个初始速率寄存器中，一个用于全速率，一个一半速率，一个用于四分之一速率。 在全速率模式下，利用来自模拟电路的所有采样。 在半速率和四分之一速率模式下，分别利用了每两个样本中的一个和四个样本中的一个。 所选样本通过核心逻辑功能转换为并行数据，其被提供与特定操作模式对应的单个时钟信号。

公开(公告)号：US20050267705A1

公开(公告)日：2005-12-01

申请号：US10709805

申请日：2004-05-28

申请人： Jeanne Bickford ,  Vernon Norman ,  Michael Ouellette ,  Mark Styduhar ,  Brian Worth

发明人： Jeanne Bickford ,  Vernon Norman ,  Michael Ouellette ,  Mark Styduhar ,  Brian Worth

IPC分类号： G01R31/28 ,  G06F19/00 ,  H01L21/66

CPC分类号： G01R31/2831 ,  H01L22/14

摘要： A method for providing quality control on wafers running on a manufacturing line is disclosed. The resistances on a group of manufacturing test structures within a wafer running on a wafer manufacturing line are initially measured. Then, an actual distribution value is obtained based on the result of the measured resistances on the group of manufacturing test structures. The difference between the actual distribution value and a predetermined distribution value is recorded. The predetermined distribution value is previously obtained based on a ground rule resistance. Next, the resistances on a group of design test structures within the wafer are measured. The measured resistances of the group of design test structures are correlated to the measured resistances of the group of manufacturing test structures in order to obtain an offset value. The resistance of an adjustable resistor circuit within the wafer is then adjusted accordingly, and subsequent wafers running on the wafer manufacturing line are also adjusted according to the offset value.

摘要翻译： 公开了一种用于对在生产线上运行的晶片进行质量控制的方法。 初始测量在晶片生产线上运行的晶片内的一组制造测试结构的电阻。 然后，基于制造试验结构体的测定电阻的结果，求出实际的分布值。 记录实际分布值与预定分布值之间的差。 基于接地规则电阻预先获得预定分布值。 接下来，测量晶片内的一组设计测试结构的电阻。 设计测试结构组的测量电阻与制造测试结构组的测量电阻相关，以获得偏移值。 然后相应地调节晶片内的可调节电阻电路的电阻，并且还根据偏移值来调整在晶片制造线上运行的后续晶片。