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    Method and system for calibrating input voltage of voltage controlled oscillator and digital interface used for calibrating input voltage
    11.
    发明申请
    Method and system for calibrating input voltage of voltage controlled oscillator and digital interface used for calibrating input voltage 失效
    用于校准压控振荡器的输入电压和用于校准输入电压的数字接口的方法和系统

    公开(公告)号：US20060208808A1

    公开(公告)日：2006-09-21

    申请号：US11368627

    申请日：2006-03-07

    申请人： Hee-mun Bang ,  Dae-ki Kim ,  Chong-ouk Kim ,  Heung-bae Lee ,  Sung-jae Jung ,  Sang-yoon Jeon

    发明人： Hee-mun Bang ,  Dae-ki Kim ,  Chong-ouk Kim ,  Heung-bae Lee ,  Sung-jae Jung ,  Sang-yoon Jeon

    IPC分类号： H03L7/00

    CPC分类号： H03L7/10 ,  Y10S331/02

    摘要： A method and a system for calibrating an input voltage of a voltage controlled oscillator and a digital interface used for calibrating the input voltage. The method includes: setting a lock detection time for tuning a signal phase; setting a lock detection voltage section; setting output frequency values at predetermine spacings; checking connection states of capacitors of the capacitor bank necessary for a lock of the output frequency values; storing information regarding the connection states of the capacitors in the output frequency values; and if one of the output frequency values is determined depending on a change of a channel, setting connection states of the capacitors according to the information regarding the connection state corresponding to the one frequency value. The capacitor bank includes: a predetermined number of capacitors having different capacitances and connected to one another in parallel; and switches connected to the capacitors in series.

    摘要翻译： 用于校准压控振荡器的输入电压的方法和系统以及用于校准输入电压的数字接口。 该方法包括：设置用于调谐信号相位的锁定检测时间; 设置锁定检测电压部分; 以预定的间距设定输出频率值; 检查用于锁定输出频率值所需的电容器组的电容器的连接状态; 将关于电容器的连接状态的信息存储在输出频率值中; 并且如果根据信道的变化确定输出频率值中的一个，则根据与一个频率值相对应的关于连接状态的信息来设置电容器的连接状态。 电容器组包括：具有不同电容并且彼此并联连接的预定数量的电容器; 并且串联连接到电容器的开关。

    MIM capacitor including ground shield layer
    12.
    发明申请
    MIM capacitor including ground shield layer 审中-公开
    MIM电容器包括接地屏蔽层

    公开(公告)号：US20060197133A1

    公开(公告)日：2006-09-07

    申请号：US11360585

    申请日：2006-02-24

    申请人： Sung-jae Jung ,  Sang-yoon Jeon ,  Hee-mun Bang ,  Kwang-du Lee ,  Heung-bae Lee

    发明人： Sung-jae Jung ,  Sang-yoon Jeon ,  Hee-mun Bang ,  Kwang-du Lee ,  Heung-bae Lee

    IPC分类号： H01L29/94

    CPC分类号： H01L23/5225 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An MIM capacitor includes a substrate, a capacitor part having a structure in which a bottom electrode, a dielectric layer and a top electrode are laminated in order, and a ground shield layer formed between the bottom electrode of the capacitor part and the substrate and connected to a predetermined ground terminal. The ground shield layer may be formed of metal or polysilicon, or a layer doped with impurities having a valence of three or five. Also, the ground shield layer has a predetermined patterned structure. Thus, it is possible to minimize power loss due to the substrate.

    摘要翻译： MIM电容器包括基板，具有依次层叠底部电极，电介质层和顶部电极的结构的电容器部分，以及形成在电容器部分的底部电极和基板之间的接地屏蔽层，并连接 到预定的接地端子。 接地屏蔽层可以由金属或多晶硅形成，或者掺杂有三价或五价杂质的层。 此外，接地屏蔽层具有预定的图案结构。 因此，可以最小化由于衬底引起的功率损耗。

    NxN multiple-input multiple-output transceiver
    14.
    发明授权
    NxN multiple-input multiple-output transceiver 失效
    NxN多输入多输出收发器

    公开(公告)号：US07848435B2

    公开(公告)日：2010-12-07

    申请号：US11543120

    申请日：2006-10-05

    申请人： Sang-yoon Jeon ,  Hee-mun Bang ,  Sung-jae Jung ,  Heung-bae Lee

    发明人： Sang-yoon Jeon ,  Hee-mun Bang ,  Sung-jae Jung ,  Heung-bae Lee

    IPC分类号： H04L1/02

    CPC分类号： H04B7/0413 ,  H04L1/06

    摘要： An N×N multiple-input multiple-output (MIMO) transceiver is provided. The transceiver includes a plurality of transceivers, each including at least one transceiver circuit; an oscillation unit which is configured to generate a differential signal which is supplied to the at least one transceiver circuit; a plurality of buffers, which are mounted in a bypass line between the at least one transceiver circuit and the oscillation unit and are configured to amplify and bypass the differential signal or input and amplify the differential signal; and a buffer control unit which is configured to control the plurality of buffers to bypass or input the differential signal.

    摘要翻译： 提供了一种N×N多输入多输出（MIMO）收发器。 收发器包括多个收发器，每个收发器包括至少一个收发器电路; 振荡单元，被配置为生成提供给所述至少一个收发器电路的差分信号; 多个缓冲器，其安装在所述至少一个收发器电路和所述振荡单元之间的旁路线路中，并且被配置为放大和旁路所述差分信号或者输入和放大所述差分信号; 以及缓冲器控制单元，其被配置为控制所述多个缓冲器来旁路或输入所述差分信号。

    Apparatus and method of stabilizing sigma-delta modulator for fractional-N phase-locked-loop
    17.
    发明授权
    Apparatus and method of stabilizing sigma-delta modulator for fractional-N phase-locked-loop 失效
    用于分数N锁相环稳定Σ-Δ调制器的装置和方法

    公开(公告)号：US07307566B2

    公开(公告)日：2007-12-11

    申请号：US11360614

    申请日：2006-02-24

    申请人： Andrew Han ,  Hee-mun Bang ,  Heung-bae Lee

    发明人： Andrew Han ,  Hee-mun Bang ,  Heung-bae Lee

    IPC分类号： H03M3/00

    CPC分类号： H03M7/3006 ,  H03L7/1976 ,  H03M7/3037 ,  H03M7/304

    摘要： A sigma-delta modulation method with low complexity is provided. To this end, in the present invention, an input signal is forwarded and an output signal is fed back to thus reduce the range of the noise transfer function of the sigma-delta modulator and to lower the frequency offset and the phase noise at low frequencies. A sigma-delta modulator for a frequency synthesizer may include one or more modulation units which are connected in series and perform a sigma-delta modulation to an input signal and a provided accumulated signal using a signal which is weighted with a feedback coefficient; and an output adder which adds an output signal from a terminal section of the modulation units and the input signal, and outputs the added signal for feedback to the modulation units.

    摘要翻译： 提供了一种低复杂度的Σ-Δ调制方法。 为此，在本发明中，输入信号被转发并且反馈输出信号，从而减小Σ-Δ调制器的噪声传递函数的范围并降低频率偏移和低频下的相位噪声 。 用于频率合成器的Σ-Δ调制器可以包括串联连接的一个或多个调制单元，并且使用利用反馈系数加权的信号对输入信号和提供的累加信号执行Σ-Δ调制; 以及输出加法器，其将来自调制单元的端子部分的输出信号和输入信号相加，并将相加的信号输出到调制单元。

    Method and system for calibrating input voltage of voltage controlled oscillator and digital interface used for calibrating input voltage
    18.
    发明授权
    Method and system for calibrating input voltage of voltage controlled oscillator and digital interface used for calibrating input voltage 失效
    用于校准压控振荡器的输入电压和用于校准输入电压的数字接口的方法和系统

    公开(公告)号：US07301406B2

    公开(公告)日：2007-11-27

    申请号：US11368627

    申请日：2006-03-07

    申请人： Hee-mun Bang ,  Dae-ki Kim ,  Chong-ouk Kim ,  Heung-bae Lee ,  Sung-jae Jung ,  Sang-yoon Jeon

    发明人： Hee-mun Bang ,  Dae-ki Kim ,  Chong-ouk Kim ,  Heung-bae Lee ,  Sung-jae Jung ,  Sang-yoon Jeon

    IPC分类号： H03L7/095 ,  H03L7/10 ,  H03L7/18 ,  G01R23/00

    CPC分类号： H03L7/10 ,  Y10S331/02

    摘要： A method and a system for calibrating an input voltage of a voltage controlled oscillator and a digital interface used for calibrating the input voltage. The method includes: setting a lock detection time for tuning a signal phase; setting a lock detection voltage section; setting output frequency values at predetermine spacings; checking connection states of capacitors of the capacitor bank necessary for a lock of the output frequency values; storing information regarding the connection states of the capacitors in the output frequency values; and if one of the output frequency values is determined depending on a change of a channel, setting connection states of the capacitors according to the information regarding the connection state corresponding to the one frequency value. The capacitor bank includes: a predetermined number of capacitors having different capacitances and connected to one another in parallel; and switches connected to the capacitors in series.

    摘要翻译： 用于校准压控振荡器的输入电压的方法和系统以及用于校准输入电压的数字接口。 该方法包括：设置用于调谐信号相位的锁定检测时间; 设置锁定检测电压部分; 以预定的间距设定输出频率值; 检查用于锁定输出频率值所需的电容器组的电容器的连接状态; 将关于电容器的连接状态的信息存储在输出频率值中; 并且如果根据信道的变化确定输出频率值中的一个，则根据与一个频率值相对应的关于连接状态的信息来设置电容器的连接状态。 电容器组包括：具有不同电容并且彼此并联连接的预定数量的电容器; 并且串联连接到电容器的开关。

    Apparatus and method of stabilizing sigma-delta modulator for fractional-N phase-locked-loop
    19.
    发明申请
    Apparatus and method of stabilizing sigma-delta modulator for fractional-N phase-locked-loop 失效
    用于分数N锁相环稳定Σ-Δ调制器的装置和方法

    公开(公告)号：US20060192704A1

    公开(公告)日：2006-08-31

    申请号：US11360614

    申请日：2006-02-24

    申请人： Andrew Han ,  Hee-mun Bang ,  Heung-bae Lee

    发明人： Andrew Han ,  Hee-mun Bang ,  Heung-bae Lee

    IPC分类号： H03M3/00

    CPC分类号： H03M7/3006 ,  H03L7/1976 ,  H03M7/3037 ,  H03M7/304

    摘要： A sigma-delta modulation method with low complexity is provided. To this end, in the present invention, an input signal is forwarded and an output signal is fed back to thus reduce the range of the noise transfer function of the sigma-delta modulator and to lower the frequency offset and the phase noise at low frequencies. A sigma-delta modulator for a frequency synthesizer may include one or more modulation units which are connected in series and perform a sigma-delta modulation to an input signal and a provided accumulated signal using a signal which is weighted with a feedback coefficient; and an output adder which adds an output signal from a terminal section of the modulation units and the input signal, and outputs the added signal for feedback to the modulation units.

    摘要翻译： 提供了一种低复杂度的Σ-Δ调制方法。 为此，在本发明中，输入信号被转发并且反馈输出信号，从而减小Σ-Δ调制器的噪声传递函数的范围并降低频率偏移和低频下的相位噪声 。 用于频率合成器的Σ-Δ调制器可以包括串联连接的一个或多个调制单元，并且使用利用反馈系数加权的信号对输入信号和提供的累加信号执行Σ-Δ调制; 以及输出加法器，其将来自调制单元的端子部分的输出信号和输入信号相加，并将相加的信号输出到调制单元。