公开(公告)号：US08509018B2

公开(公告)日：2013-08-13

申请号：US12855289

申请日：2010-08-12

申请人： Atul Katoch

发明人： Atul Katoch

IPC分类号： G11C7/02

CPC分类号： G11C11/4091

摘要： A circuit having a sensing circuit and at least one of a first node and a second node is described. The sensing circuit includes a pair of a first type transistors and a pair of a second type transistors. Each transistor of the pair of the first type transistors is coupled in series with a transistor of the pair of the second type transistors. The first node has a first voltage and is coupled to each bulk of each transistor of the pair of the first type transistors. The second node has a second voltage and is coupled to each bulk of each transistor of the pair of the second type transistors.

摘要翻译： 描述具有感测电路和第一节点和第二节点中的至少一个的电路。 感测电路包括一对第一类型晶体管和一对第二类型晶体管。 该对第一类型晶体管中的每个晶体管与该对第二类型晶体管的晶体管串联耦合。 第一节点具有第一电压并且耦合到该对第一类型晶体管的每个晶体管的每个主体。 第二节点具有第二电压并且耦合到该对第二类型晶体管的每个晶体管的每个主体。

公开(公告)号：US08295112B2

公开(公告)日：2012-10-23

申请号：US12731625

申请日：2010-03-25

申请人： Atul Katoch ,  Mayank Tayal

发明人： Atul Katoch ,  Mayank Tayal

IPC分类号： G11C7/02

CPC分类号： G11C7/065 ,  G11C7/08

摘要： Embodiments of the invention are related to sense amplifiers. In an embodiment involving a sense amplifier used with a memory cell, signals BL, ZBL, SN and SP are pre-charged and equalized to a voltage reference, e.g., Vref, using an equalizing signal. A compensation signal, e.g., SAC, is applied to compensate for the mismatch between transistors in the sense amplifier. The word line WL is activated to connect the memory cell to a bit line, e.g., bit line ZBL. Because the memory cell shares the charge with the connected bit line ZBL, it causes a differential signal to be developed between bit lines BL and ZBL. When enough split between bit lines BL and ZBL is developed, signals SP and SAE are raised to VDD (while signal SN has been lowered to VSS) to turn on the sense amplifier and allow it to function as desire. Other embodiments and exemplary applications are also disclosed.

摘要翻译： 本发明的实施例涉及读出放大器。 在涉及与存储器单元一起使用的读出放大器的实施例中，使用均衡信号将信号BL，ZBL，SN和SP预充电并均衡到电压参考值，例如Vref。 施加补偿信号，例如SAC，以补偿读出放大器中的晶体管之间的失配。 字线WL被激活以将存储器单元连接到位线，例如位线ZBL。 由于存储单元与所连接的位线ZBL共享电荷，所以在位线BL和ZBL之间产生差分信号。 当位线BL和ZBL之间的足够的分割被开发时，信号SP和SAE升高到VDD（当信号SN已经降低到VSS时），以使得读出放大器接通，并使其能够按需要起作用。 还公开了其它实施例和示例性应用。

公开(公告)号：US20090013116A1

公开(公告)日：2009-01-08

申请号：US12279330

申请日：2007-02-06

申请人： Kark Oskar Svanell ,  Daniel J. Boijort ,  Atul Katoch

发明人： Kark Oskar Svanell ,  Daniel J. Boijort ,  Atul Katoch

IPC分类号： G06F13/372

CPC分类号： H04L25/493

摘要： A method (100) is disclosed for communicating data over a data communication bus (310) comprising a first conductor (312) and a set of further conductors (314). The method (300) comprises providing the first conductor (312) with a first signal transition (210) for signalling the start of a first data communication period (T1); and providing a further conductor (314), after a predefined delay with respect to the provision of the first signal transition (210), with a delayed signal transition (220), the predefined delay defining a first data value. Consequently, the method of the present invention provides a data encoding technique for data communication over a bus that requires less switching activity than other encoding techniques such as pulse width modulation encoding. The present invention further discloses a data communication device (400), a data reception device (500) and a system (300) including these devices, all implementing various aspects of the aforementioned method.

摘要翻译： 公开了一种用于在包括第一导体（312）和一组另外的导体（314）的数据通信总线（310）上传送数据的方法（100）。 方法（300）包括提供第一导体（312）以用于发信号通知第一数据通信周期（T1）的开始的第一信号转换（210）。 以及提供另一个导体（314），在相对于提供第一信号转换（210）的预定义延迟之后，延迟信号转换（220），所述预定延迟定义第一数据值。 因此，本发明的方法提供了一种用于总线上的数据通信的数据编码技术，其需要比诸如脉冲宽度调制编码的其它编码技术更少的切换活动。 本发明还公开了一种数据通信设备（400），数据接收设备（500）和包括这些设备的系统（300），全部实现了上述方法的各个方面。

公开(公告)号：US20080284491A1

公开(公告)日：2008-11-20

申请号：US11911881

申请日：2006-04-20

申请人： Hendricus J.M. Veendrick ,  Atul Katoch

发明人： Hendricus J.M. Veendrick ,  Atul Katoch

IPC分类号： H03K17/687

CPC分类号： H03K19/0019

摘要： An integrated circuit (10) comprises a plurality of functional blocks (101, 102, 103), each of the functional blocks (101, 102, 103) being coupled between a first power supply line (110) and a second power supply line (120). A first functional block (101) is coupled to the first power supply line (110) via a first conductive path including a first switch (131) and a second functional block (102) is coupled to the first power supply line (110) via a second conductive path including a second switch (132), the first switch (131) and the second switch (132) being arranged to respectively disconnect the first functional block (101) and the second functional block (102) from the first power supply line (110) for switching said functional blocks (101; 102) from an active mode to a standby mode. The IC (10) comprises a further switch (141) having a first terminal coupled to a node (121) of the first conductive path between the first switch (131) and the first functional block (101) and a second terminal coupled to a node (122) of the second conductive path between the second switch (132) and the second functional block (102). The further switch (141) has a control terminal responsive to an enable signal indicating that the first switch (131) and the second switch (132) are disabled, thus allowing the recycling of charge between the first functional block (101) and the second functional block (102).

摘要翻译： 集成电路（10）包括多个功能块（101,102,103），每个功能块（101,102,103）被耦合在第一电源线（110）和第二电源线（ 120）。 第一功能块（101）经由包括第一开关（131）的第一导电路径耦合到第一电源线（110），并且第二功能块（102）经由第一电源线（110）经由 包括第二开关（132）的第二导电路径，所述第一开关（131）和所述第二开关（132）被布置成分别将所述第一功能块（101）和所述第二功能块（102）与所述第一电源 线路（110），用于将所述功能块（101; 102）从活动模式切换到待机模式。 IC（10）包括另外的开关（141），其具有耦合到第一开关（131）和第一功能块（101）之间的第一导电路径的节点（121）的第一端子和耦合到第一端子 在第二开关（132）和第二功能块（102）之间的第二导电路径的节点（122）。 另外的开关（141）具有响应于指示第一开关（131）和第二开关（132）被禁用的使能信号的控制端子，从而允许在第一功能块（101）和第二开关 功能块（102）。

公开(公告)号：US07439759B2

公开(公告)日：2008-10-21

申请号：US10558145

申请日：2004-05-17

申请人： Atul Katoch ,  Manish Garg ,  Evert Seevinck ,  Hendricus Joseph Maria Veendrick

发明人： Atul Katoch ,  Manish Garg ,  Evert Seevinck ,  Hendricus Joseph Maria Veendrick

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： G06F13/4072

摘要： As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to poor performance due to poor RC response at the receiving of the wire, which may even result in failure in very noisy environments. An adaptive threshold scheme is proposed in which receiver switching thresholds are adjusted according to the detected noise in bus lines. These noise levels are dependent on both the front-end processing (transistor performance) as well as on the backend processing (metal resistance, capacitance, width and spacing). The circuit therefore automatically compensates for process variations.

摘要翻译： 随着技术的发展，片上互连变得越来越窄，这种互连的高度并没有随宽度而线性缩放。 这导致与相邻导线的耦合电容的增加，导致更高的串扰。 由于在接收线路时RC响应差，导致性能差，甚至可能导致非常嘈杂的环境中的故障​​。 提出了一种自适应阈值方案，其中接收机切换阈值根据总线线路中检测到的噪声进行调整。 这些噪声水平取决于前端处理（晶体管性能）以及后端处理（金属电阻，电容，宽度和间距）。 因此，电路自动补偿过程变化。

公开(公告)号：US07355443B2

公开(公告)日：2008-04-08

申请号：US10519767

申请日：2003-06-17

申请人： Katarzyna Leijten-Nowak ,  Atul Katoch

发明人： Katarzyna Leijten-Nowak ,  Atul Katoch

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： G06F17/5068 ,  H01L27/0207 ,  H01L27/118

摘要： An integrated circuit (300) has a regular grid formed by substantially identical building blocks (100a-i). To avoid possible routing conflicts around the edges of the integrated circuit (300), which can be introduced by the use of a single type of an asymmetric building block, the integrated circuit (300) is extended with routing cells (200) that provide routing at the edges of the grid that are uncovered by the routing networks of the building blocks (100a-i). The routing cells (200) and the switch cell (250) are combined with a first routing structure (330) and a second routing structure (340) to form a routing network (280) surrounding the grid of the integrated circuit (300). Consequently, an integrated circuit (300) is presented that comprises only a single type of building block (100a-i) but still has a fully symmetric routing architecture.

摘要翻译： 集成电路（300）具有由基本上相同的构建块（100a-i）形成的规则网格。 为了避免可以通过使用单一类型的非对称构建块引入的集成电路（300）的边缘周围的可能的路由冲突，集成电路（300）被扩展，路由单元（200）提供路由 在由所述构建块（100a）的路由网络未覆盖的所述网格的边缘处。 路由单元（200）和交换单元（250）与第一路由结构（330）和第二路由结构（340）组合以形成围绕集成电路（300）的网格的路由网络（280）。 因此，提出了仅包括单一类型的构建块（100a-i）但仍具有完全对称的路由架构的集成电路（300）。

公开(公告)号：US20070052443A1

公开(公告)日：2007-03-08

申请号：US10556005

申请日：2004-05-07

申请人： Atul Katoch ,  Sanjeev Jain ,  Rinze Meijer

发明人： Atul Katoch ,  Sanjeev Jain ,  Rinze Meijer

IPC分类号： H03K19/003

CPC分类号： H03K19/00361 ,  H03K19/0027

摘要： A buffer circuit (31), for example a repeater or receiver circuit for a signal wire of an on-chip bus, receives an input signal, and produces an output signal. The buffer circuit (31) comprises a first inverting stage (7) and a second inverter stage (9). The second inverting stage (9) provides the drive for the output (5). The first inverting stage (7) has additional circuitry (15, 17, 19, 21, 23, 25, 27, 29) for controlling the strengths of the pull up path and the pull down path. The pull up/down paths are dynamically controlled according to the status of one or more aggressor signals. In one embodiment the switching threshold is lowered only in the worst case delay scenario, i.e. when the signal wire (3) is at a different logic level to the aggressor signals. In another embodiment, the switching threshold is raised when the signal wire and aggressor signals are all at the same logic level, thereby reducing crosstalk.

摘要翻译： 缓冲电路（31），例如用于片上总线的信号线的中继器或接收器电路，接收输入信号，并产生输出信号。 缓冲电路（31）包括第一反相级（7）和第二反相器级（9）。 第二反相级（9）为输出（5）提供驱动。 第一反相级（7）具有用于控制上拉路径和下拉路径的强度的附加电路（15,17,19,21,23,25,27,29）。 根据一个或多个攻击者信号的状态来动态地控制上拉/下拉路径。 在一个实施例中，切换阈值仅在最坏情况下延迟情况下降低，即当信号线（3）与侵略者信号处于不同的逻辑电平时。 在另一个实施例中，当信号线和侵扰器信号都处于相同的逻辑电平时，切换阈值升高，从而减少串扰。

公开(公告)号：US20070013429A1

公开(公告)日：2007-01-18

申请号：US10556113

申请日：2004-08-07

申请人： Atul Katoch ,  Rinze Meijer ,  Sanjeev Jain

发明人： Atul Katoch ,  Rinze Meijer ,  Sanjeev Jain

IPC分类号： H03K5/08

CPC分类号： H03K19/00346 ,  H03K5/08 ,  H04L25/085

摘要： A clamper circuit (1) receives an input signal (3) from the signal wire being clamped, i.e. the victim wire. The clamper circuit (1) also receives aggressor signals (5, 7) from aggressor wires, the aggressor wires being the signal wires that can potentially induce crosstalk on the victim wire. An output signal (9), for clamping the victim wire, is selectively enabled based on the logic states of the input signal (3) and the aggressor signals (5, 7). In addition to selectively providing a clamping signal, the clamper circuit (1) also has the advantage of accelerating the switching of the victim wire when an opposite transition occurs on the aggressors and victim wire at the same time, thereby reducing worst case delay and improving the signal integrity.

摘要翻译： 钳位电路（1）从被钳位的信号线接收输入信号（3），即受害线。 夹持器电路（1）还从侵扰线接收侵扰信号（5,7），侵略线是可能在受害线上潜在地诱发串扰的信号线。 基于输入信号（3）和侵扰信号（5,7）的逻辑状态，有选择地使能用于钳位受干线的输出信号（9）。 除了选择性地提供钳位信号之外，钳位电路（1）还具有在侵入者和受害线同时发生相反转变时加速受害线的切换的优点，从而减少最坏情况的延迟和改善 信号完整性。

公开(公告)号：US20060244488A1

公开(公告)日：2006-11-02

申请号：US10525865

申请日：2003-07-31

申请人： Atul Katoch ,  Evert Seevinck ,  Hendricus Veendrick

发明人： Atul Katoch ,  Evert Seevinck ,  Hendricus Veendrick

IPC分类号： H03K19/0175

CPC分类号： H04L25/08 ,  H04L25/026 ,  H04L25/0272 ,  H04L25/0294

摘要： An electronic data processing circuit uses current mode signalling on a communication conductor, wherein a receiver supplies current to the communication conductor to try and keep a voltage on the conductor constant and measures the current that is needed to do so. A transition coding circuit is coupled between a data source circuit and the communication conductor, for driving the communication conductor in a first state in pulses in response to transitions in the logic signal and in a second state outside the pulses. The level that is used for indicating no change is selected so the current that needs to be supplied by the receiver is smaller when no change is signalled than when a change is signalled. Preferably only a nearly zero quiescent current is needed when there is no change.

摘要翻译： 电子数据处理电路在通信导体上使用电流模式信号，其中接收器向通信导体提供电流以尝试并保持导体上的电压恒定并且测量所需的电流。 转换编码电路耦合在数据源电路和通信导体之间，用于响应于逻辑信号中的转换和在脉冲之外的第二状态以脉冲方式驱动通信导体处于第一状态。 选择用于指示没有变化的电平，所以当没有发出变化时，接收器需要提供的电流比发出变化时更小。 当没有变化时，最好只需要几乎零静态电流。

公开(公告)号：US09324412B2

公开(公告)日：2016-04-26

申请号：US13791025

申请日：2013-03-08

申请人： Atul Katoch ,  Mayank Tayal

发明人： Atul Katoch ,  Mayank Tayal

IPC分类号： G11C7/22 ,  G11C11/419 ,  G11C7/08 ,  G11C7/12

CPC分类号： G11C11/419 ,  G11C7/08 ,  G11C7/12

摘要： A memory circuit includes a memory cell and a data circuit. In a write operation of the memory cell, the data circuit is configured to provide a first write logical value to the first output of the data circuit and to provide a second write logical value to the second output of the data circuit. The first write logical value is different from the second write logical value. In a read operation of the memory cell, the data circuit is configured to provide a same logical value to the first output and the second output of the data circuit.

摘要翻译： 存储电路包括存储单元和数据电路。 在存储单元的写入操作中，数据电路被配置为向数据电路的第一输出提供第一写入逻辑值，并向数据电路的第二输出提供第二写入逻辑值。 第一个写入逻辑值与第二个写入逻辑值不同。 在存储单元的读取操作中，数据电路被配置为向数据电路的第一输出和第二输出提供相同的逻辑值。