公开(公告)号：US06576318B2

公开(公告)日：2003-06-10

申请号：US09873189

申请日：2001-06-05

Applicant: Heon Lee ,  Robert Bicknell-Tassius

Inventor： Heon Lee ,  Robert Bicknell-Tassius

IPC: B32B302

CPC classification number: G11B7/26 ,  G11B7/24056 ,  G11B7/266 ,  Y10T428/21 ,  Y10T428/24355

Abstract: A method of forming a crystalline, phase-change layer that remains atomically smooth on its surface. Also, an atomically smooth, crystalline, phase-change layer made according to this method. The method can include forming a phase-change layer over a substrate, forming a thick capping layer over the phase-change layer, changing the phase-change layer from an amorphous phase to a crystalline phase, removing the thick capping layer, and forming a thin capping layer over the phase-change layer.

公开(公告)号：US06440820B1

公开(公告)日：2002-08-27

申请号：US09860452

申请日：2001-05-21

Applicant: Heon Lee ,  Chung-Ching Yang ,  Peter Hartwell

Inventor： Heon Lee ,  Chung-Ching Yang ,  Peter Hartwell

IPC: H01L2130

CPC classification number: G11B9/1418 ,  B82Y10/00 ,  G01Q80/00 ,  G11B9/1463

Abstract: An improved process flow for an atomic resolution storage (ARS) system deposits conductive electrodes, together with a protective layer, on a media side of a rotor wafer before most of other device processing, thus preserving a surface for ARS storage media from subsequent wafer thinning process. CMOS circuitry is also formed in a stator wafer at a later stage. Therefore, the CMOS circuitry is less likely to be damaged by heat processing. In addition, processing of the media side of the rotor wafer may be performed with loosened thermal budget. Finally, because the media side of the rotor wafer is processed before wafer bonding of the rotor wafer and the stator wafer, there is less probability of degradation of the wafer bonding. Therefore, device yield may be enhanced, leading to lower manufacturing cost.

Abstract translation: 原子分辨率存储（ARS）系统的改进的处理流程在其他器件处理之前大部分其它器件处理之前，将转移晶片的介质侧上的导电电极与保护层一起放置在一起，从而保留了ARS存储介质从后续晶片变薄的表面 处理。 在稍后阶段也在定子晶片中形成CMOS电路。 因此，CMOS电路不太可能被热处理所损坏。 此外，可以以松散的热量预算来执行转子晶片的介质侧的处理。 最后，因为转子晶片的介质侧在转子晶片和定子晶片的晶片接合之前被处理，所以晶片键合的劣化的可能性降低。 因此，可以提高装置产量，导致制造成本降低。

公开(公告)号：US06440793B1

公开(公告)日：2002-08-27

申请号：US09757514

申请日：2001-01-10

Applicant: Ramachandra Divakaruni ,  Heon Lee ,  Jack A. Mandelman ,  Carl J. Radens ,  Jai-Hoon Sim

Inventor： Ramachandra Divakaruni ,  Heon Lee ,  Jack A. Mandelman ,  Carl J. Radens ,  Jai-Hoon Sim

IPC: H01L218242

CPC classification number: H01L27/10841 ,  H01L21/2255 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

Abstract: An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.

公开(公告)号：US06355520B1

公开(公告)日：2002-03-12

申请号：US09374537

申请日：1999-08-16

Applicant: Youngjin Park ,  Heon Lee

Inventor： Youngjin Park ,  Heon Lee

IPC: H01L21336

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10876

Abstract: In accordance with the present invention, a method for forming gate conductors in 4F2 area stacked capacitor memory cells includes the steps of forming a buried bit line in a substrate, forming an active area above and in contact with the buried bit line and separating portions of the active area by forming a dielectric material in trenches around the portions of the active area. Portions of the dielectric material are removed adjacent to and selective to the portions of the active area. A first portion of a gate conductor is formed in locations from which the portion of dielectric material is removed, and a second portion of the gate conductor is formed on a top surface of the dielectric material and in contact with the first portion of the gate conductor. Stacked capacitors are formed such that the gate conductor activates an access transistor formed in the portions of the active area. A layout is also included.

Abstract translation: 根据本发明，一种在4F2区域层叠电容器存储单元中形成栅极导体的方法包括以下步骤：在衬底中形成掩埋位线，在掩埋位线上方形成有源区，并与掩埋位线接触并分离部分 有源区域通过在有源区域的部分周围的沟槽中形成电介质材料。 电介质材料的一部分被移除并且与有源区的部分有选择性地去除。 栅极导体的第一部分形成在绝缘材料部分被去除的位置，并且栅极导体的第二部分形成在电介质材料的顶表面上并与栅极导体的第一部分接触 。 堆叠的电容器形成为使得栅极导体激活形成在有源区域的部分中的存取晶体管。 还包括布局。

公开(公告)号：US06294436B1

公开(公告)日：2001-09-25

申请号：US09374538

申请日：1999-08-16

Applicant: Youngjin Park ,  Heon Lee

Inventor： Youngjin Park ,  Heon Lee

IPC: H01L2120

CPC classification number: H01L27/10852

Abstract: In accordance with the present invention, a method for expanding holes for the formation of stacked capacitors is described and claimed. The method includes the steps of providing a planarized dielectric layer for forming bottom electrodes of the stacked capacitors, forming a first dielectric layer on the planarized dielectric layer, forming a second dielectric layer on the first dielectric layer. The second dielectric layer is selectively etchable relative to the first dielectric layer. The steps of etching the second dielectric layer to form holes for forming the bottom electrodes and isotropically etching the second dielectric layer to expand the holes for forming the bottom electrodes are also included.

Abstract translation: 根据本发明，描述并要求保护用于形成叠层电容器的孔的方法。 该方法包括以下步骤：提供用于形成层叠电容器的底部电极的平坦化介电层，在平坦化电介质层上形成第一电介质层，在第一电介质层上形成第二电介质层。 第二电介质层相对于第一介电层可选择性地蚀刻。 还包括蚀刻第二电介质层以形成用于形成底部电极的孔和各向同性蚀刻第二电介质层以扩大用于形成底部电极的孔的步骤。

公开(公告)号：US20060086986A1

公开(公告)日：2006-04-27

申请号：US11255458

申请日：2005-10-20

Applicant: Hang Liao ,  Zhizhang Chen ,  Alexander Govyadinov ,  Leslie Szepesi ,  Heon Lee

Inventor： Hang Liao ,  Zhizhang Chen ,  Alexander Govyadinov ,  Leslie Szepesi ,  Heon Lee

IPC: H01L29/76

CPC classification number: B82Y10/00 ,  G11B9/08 ,  G11B9/14 ,  G11B9/1409 ,  G11B9/1418 ,  G11B9/1436 ,  G11B11/08

Abstract: A storage device includes a first semiconducting layer having a p-dopant and a second semiconducting layer having an n-dopant, disposed on the first semiconducting layer forming a junction between the first and the second semiconducting layers. The storage device also includes a charge trapping structure disposed on the second semiconducting layer and a conductive gate, wherein the conductive gate and the charge trapping structure move relative to the other, wherein an electric field applied across the second semiconducting layer and the conductive gate traps charge in the charge trapping structure.

公开(公告)号：US06937506B2

公开(公告)日：2005-08-30

申请号：US10753539

申请日：2004-01-08

Applicant: Thomas C. Anthony ,  Frederick A. Perner ,  Heon Lee

Inventor： Thomas C. Anthony ,  Frederick A. Perner ,  Heon Lee

IPC: G11C11/02 ,  G11C11/14 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

CPC classification number: G11C11/15

Abstract: A random access memory (MRAM) that includes a magnetic memory cell that is switchable between two states under the influence of a magnetic field. The MARAM also includes an electrical bit line coupled to the magnetic memory cell for generating the magnetic field. The electrical bit line includes a conductive component and a magnetic component to guide magnetic flux associated with the magnetic field towards the magnetic memory cell. A thermal insulator is positioned between the conductive portion and the magnetic memory cell, and the magnetic component has at least one guiding portion that extends from the conductive component towards the magnetic memory cell to guide the magnetic flux around at least a portion of the thermal insulator.

Abstract translation: 一种随机存取存储器（MRAM），其包括在磁场影响下在两个状态之间切换的磁存储单元。 MARAM还包括耦合到磁存储单元的电位线，用于产生磁场。 电位线包括导电部件和磁性部件，以将与磁场相关联的磁通量引向磁存储器单元。 热绝缘体位于导电部分和磁存储单元之间，并且磁性部件具有至少一个引导部分，该引导部分从导电部件朝向磁存储器单元延伸，以引导围绕热绝缘体的至少一部分的磁通量 。

公开(公告)号：US20050176206A1

公开(公告)日：2005-08-11

申请号：US11104997

申请日：2005-04-13

Applicant: Manish Sharma ,  Thomas Anthony ,  Heon Lee

Inventor： Manish Sharma ,  Thomas Anthony ,  Heon Lee

IPC: H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/48 ,  H01L21/50 ,  H01L43/12

CPC classification number: H01L43/12

Abstract: An aspect of the present invention is a method of forming a contact in a thin-film device. The method includes forming a liftoff stencil, depositing at least one material through the liftoff stencil, removing a portion of the liftoff stencil depositing a dielectric material, planarizing the dielectric material thereby exposing a portion of the at least one material and depositing a conductor material in contact with the exposed portion of the at least one material.

Abstract translation: 本发明的一个方面是在薄膜器件中形成接触的方法。 该方法包括形成剥离模板，通过提升模板沉积至少一种材料，去除沉积介电材料的剥离模板的一部分，平坦化介电材料，从而暴露至少一种材料的一部分并将导体材料沉积在 与所述至少一种材料的暴露部分接触。

公开(公告)号：US20050170628A1

公开(公告)日：2005-08-04

申请号：US10770083

申请日：2004-01-31

Applicant: Manish Sharma ,  Thomas Anthony ,  Heon Lee

Inventor： Manish Sharma ,  Thomas Anthony ,  Heon Lee

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/44 ,  H01L43/12

CPC classification number: H01L21/0331 ,  H01L21/0272 ,  H01L21/31144 ,  H01L43/12 ,  Y10S438/951

Abstract: An aspect of the present invention is a method of forming a contact in a thin-film device. The method includes forming a liftoff stencil, depositing at least one material through the liftoff stencil, removing a portion of the liftoff stencil, forming a re-entrant profile with the remaining portion of the liftoff stencil and depositing a conductor material in contact with the at least one material on the re-entrant profile.

Abstract translation: 本发明的一个方面是在薄膜器件中形成接触的方法。 该方法包括形成剥离模板，将至少一种材料沉积通过剥离模板，去除剥离模板的一部分，与剥离模板的剩余部分形成重新进入的模型并且沉积导体材料与所述脱模模板接触。 至少一个材料在入口轮廓。

公开(公告)号：US20050088174A1

公开(公告)日：2005-04-28

申请号：US10692694

申请日：2003-10-27

Applicant: Seung Lee ,  Heon Lee ,  Byung Oh

Inventor： Seung Lee ,  Heon Lee ,  Byung Oh

IPC: G01R33/035 ,  G01R33/02

CPC classification number: G01R33/0356

Abstract: Disclosed a SQUID (Superconducting QUantum Interference Device) sensor using an auxiliary sensor, including: a SQUID sensing unit having a SQUID and a first feedback coil for creating a magnetic field at a periphery of the SQUID; an auxiliary sensor having a lower magnetic sensitivity and a higher operation range than the SQUID sensing unit; and a sensor reading unit for operating the SQUID sensing unit and the auxiliary sensor to read out a signal of the SQUID and at the same time, supplying the SQUID sensing unit with an offset magnetic field through the first feedback coil.

Abstract translation: 公开了一种使用辅助传感器的SQUID（超导量子干涉仪）传感器，包括：具有SQUID的SQUID感测单元和用于在SQUID的周边产生磁场的第一反馈线圈; 辅助传感器，其具有比SQUID感测单元更低的灵敏度和更高的操作范围; 以及传感器读取单元，用于操作SQUID感测单元和辅助传感器以读出SQUID的信号，并且同时向SQUID感测单元提供穿过第一反馈线圈的偏移磁场。