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公开(公告)号：US20180095722A1
公开(公告)日：2018-04-05
申请号：US15282021
申请日：2016-09-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Le Zheng , John Paul Strachan
CPC classification number: G06F7/523 , G06F7/5443 , G06F2207/4802 , G06F2207/4828 , G11C13/0007 , G11C13/0028 , G11C13/004
Abstract: In some examples, a method may be performed by a multiply-accumulate circuit. As part of the method a row driver of the multiply-accumulate circuit may drive a row value line based on an input vector bit of an input vector received by the row driver. The row driver may also drive a row line that controls a corresponding memristor according to the input vector bit. The corresponding memristor may store a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation. The method may further include a sense amplifier generating an output voltage based on a current output from the corresponding memristor and counter circuitry adjusting a counter value that represents a running total of the multiply-accumulate operation based on the row value line, the output voltage generated by the sense amplifier, or a combination of both.
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公开(公告)号：US20180025790A1
公开(公告)日：2018-01-25
申请号：US15216589
申请日：2016-07-21
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Emmanuelle J. Merced Grafals , Brent Buchanan , Le Zheng
CPC classification number: G11C29/789 , G11C13/0021 , H01L45/04 , H01L45/16
Abstract: Examples include a resistive random access memory (RRAM) array to support a redundant column. Some examples include an RRAM cell at a cross point of a column line and a row line of the RRAM array. A first column line may be coupled to a first input of a first current-steering multiplexer and the first current-steering multiplexer may have an output coupled to a first current sense amplifier and a select input coupled to a first column select signal. A second column line may be coupled to a second input of the first current-steering multiplexer and coupled to a first input of a second current-steering multiplexer. The second current-steering multiplexer may have an output coupled to a second current sense amplifier and a select input coupled to a second column select signal. A third column line may be coupled to a second input of the second current-steering multiplexer.
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公开(公告)号：US11507761B2
公开(公告)日：2022-11-22
申请号：US16072279
申请日：2016-02-25
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Le Zheng
Abstract: In one example in accordance with the present disclosure a device is described. The device includes at least two memristive cells. Each memristive cell includes a memristive element to store one component of a complex weight value. The device also includes a real input multiplier coupled to the memristive element to multiply an output signal of the memristive element with a real component of an input signal. An imaginary input multiplier of the device is coupled to the memristive element to multiply the output signal of the memristive element with an imaginary component of the input signal.
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公开(公告)号：US11158370B2
公开(公告)日：2021-10-26
申请号：US16065364
申请日：2016-01-26
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Emmanuelle J. Merced Grafals , Brent Buchanan , Le Zheng
Abstract: In one example in accordance with the present disclosure a memristive bit cell is described. The memristive bit cell includes a memristive device switchable between states. The memristive device is to store information. The memristive bit cell also includes a first switch regulating component coupled to the memristive device. The first switch regulating component enforces compliance of the memristive device with a first property threshold when switching between states in a first direction. The first property threshold corresponds to a state of the memristive device. The memristive bit cell also includes a second switch regulating component coupled to the memristive device. The second switch regulating component enforces compliance of the memristive device with a second property threshold when switching between states in a second direction. The second property threshold corresponds to a state of the memristive device.
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公开(公告)号：US10593403B2
公开(公告)日：2020-03-17
申请号：US16073902
申请日：2016-02-23
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Le Zheng
Abstract: A memristive array includes a number of bit cells, each bit cell including a memristive element and a selecting transistor serially coupled to the memristive element. The array also includes a waveform generation device coupled to the number of bit cells. The waveform generation device generates a shaped waveform to be applied to the number of bit cells to switch a state of the memristive element. The waveform generation device passes the shaped waveform to gates of the selecting transistors of the number of bit cells.
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Patent Agency Ranking
公开(公告)号：US20190235458A1
公开(公告)日：2019-08-01
申请号：US16354076
申请日：2019-03-14
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Brent Buchanan , John Paul Strachan , Le Zheng
IPC: G05B19/045 , G11C15/04
CPC classification number: G05B19/045 , G05B2219/23289 , G11C7/1006 , G11C15/04
Abstract: An example finite state machine may include a content-addressable memory. The content-addressable memory may include blocks that respectively store input-terms of the finite state machine. The finite state machine may be configured to, for each received input: select a subset of the blocks of the content addressable memory to enable for searching, the subset being selected based on a current state of the finite state machine, and determine a next state of the finite state machine by searching the currently enabled subset of blocks of the content addressable memory based on the input.
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公开(公告)号：US20190114141A1
公开(公告)日：2019-04-18
申请号：US16218636
申请日：2018-12-13
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Brent Buchanan , Le Zheng , John Paul Strachan
Abstract: In some examples, a method may be performed by a multiply-accumulate circuit. As part of the method a row driver of the multiply-accumulate circuit may drive a row value line based on an input vector bit of an input vector received by the row driver. The row driver may also drive a row line that controls a corresponding memristor according to the input vector bit. The corresponding memristor may store a weight value bit of a weight value to apply to the input vector for a multiply-accumulate operation. The method may further include a sense amplifier generating an output voltage based on a current output from the corresponding memristor and counter circuitry adjusting a counter value that represents a running total of the multiply-accumulate operation based on the row value line, the output voltage generated by the sense amplifier, or a combination of both.
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公开(公告)号：US20190043577A1
公开(公告)日：2019-02-07
申请号：US16073902
申请日：2016-02-23
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Le Zheng
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0028 , G11C13/003 , G11C2013/0071 , G11C2013/0092 , G11C2213/79
Abstract: In one example in accordance with the present disclosure a memristive array is described. The memristive array includes a number of bit cells, each bit cell including a memristive element and a selecting transistor serially coupled to the memristive element. The array also includes a waveform generation device coupled to the number of bit cells. The waveform generation device generates a shaped waveform to be applied to the number of bit cells to switch a state of the memristive element. The waveform generation device passes the shaped waveform to gates of the selecting transistors of the number of bit cells.
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公开(公告)号：US20190043573A1
公开(公告)日：2019-02-07
申请号：US16073922
申请日：2016-02-24
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Le Zheng , John Paul Strachan
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C11/2297 , G11C13/0002 , G11C13/0007 , G11C13/0021 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/0038 , G11C13/004 , G11C29/50012 , G11C2013/0045 , G11C2013/0071 , G11C2013/0073 , G11C2213/79
Abstract: In one example in accordance with the present disclosure a control circuit is described. The control circuit includes a source following component to receive an input voltage and output a switching voltage. The circuit also includes an input leg of a current mirror coupled to the source following component. The input leg of the current mirror replicates the switching voltage to an output leg of the current mirror of a memristive bit cell. The circuit also includes a number of current control components. At least one of the current control components enforces a constant current through the source following component and other current control components maintain the input leg of the current mirror and the output leg of the current mirror at the same current.
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公开(公告)号：US20180095748A1
公开(公告)日：2018-04-05
申请号：US15281280
申请日：2016-09-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Brent Buchanan , Le Zheng
CPC classification number: G06F9/3001 , G06F9/30 , G06N3/04 , G06N3/0635
Abstract: An example device may include multiply-accumulate circuitry and voltage-tracking modulator circuitry. The multiply-accumulate circuitry may be to increase and decrease an accumulation voltage held by an accumulator based on a number of input signals. The voltage-tracking modulator circuitry may be to generate an output signal based on the accumulation voltage, wherein the output signal is a continuous-time binary signal that tracks changes of the accumulation voltage by varying pulse widths of the output signal. The example device may be used as a neuron in a neural network.
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