公开(公告)号：US20090267114A1

公开(公告)日：2009-10-29

申请号：US12295104

申请日：2007-03-23

申请人： Tatsuo Nakayama ,  Yuji Ando ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Murase ,  Naotaka Kuroda

发明人： Tatsuo Nakayama ,  Yuji Ando ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Murase ,  Naotaka Kuroda

IPC分类号： H01L29/772 ,  H01L29/205

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/8128

摘要： A field effect transistor 100 includes a group III-V nitride semiconductor layer structure containing a hetero junction, a source electrode 105 and a drain electrode 106 formed on the group III-V nitride semiconductor layer structure to be spaced apart from each other; a gate electrode 110 arranged between the source electrode 105 and the drain electrode 106, and an insulating layer 107 provided over, and in contact with, the group III-V nitride semiconductor layer structure in a region between the gate electrode 110 and the drain electrode 106 or in a region between the source electrode 105 and the gate electrode 110. A portion of the gate electrode 110 is buried in the group III-V nitride semiconductor layer structure, and a side edge of the gate electrode in an interface of the group III-V nitride semiconductor layer and the insulating layer 107 is spaced apart from the gate electrode 110.

摘要翻译： 场效应晶体管100包括在III-V族氮化物半导体层结构上彼此间隔开的含有异质结的III-V族氮化物半导体层结构，源电极105和漏电极106。 布置在源电极105和漏电极106之间的栅电极110以及在栅电极110和漏电极之间的区域中设置在III-V族氮化物半导体层结构上并与III-V族氮化物半导体层结构接触的绝缘层107 106或源极电极105和栅电极110之间的区域中。栅电极110的一部分被掩埋在III-V族氮化物半导体层结构中，并且栅极电极在该组的界面中的侧边缘 III-V族氮化物半导体层和绝缘层107与栅电极110间隔开。

公开(公告)号：US08716835B2

公开(公告)日：2014-05-06

申请号：US13124873

申请日：2009-10-16

申请人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Kazuki Ota

发明人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Kazuki Ota

IPC分类号： H01L29/66 ,  H01L29/737 ,  H01L29/20

CPC分类号： H01L29/7371 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/475 ,  H01L29/66318

摘要： A bipolar transistor is provided with an emitter layer, a base layer and a collector layer. The emitter layer is formed above a substrate and is an n-type conductive layer including a first nitride semiconductor. The base layer is formed on the emitter layer and is a p-type conductive including a second nitride semiconductor. The collector layer is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed such that a crystal growth direction to the substrate surface is parallel to a substrate direction of [000-1]. The third nitride semiconductor contains InycAlxcGa1-xc-ycN (0•xc•1, 0•yc•1, 0

摘要翻译： 双极晶体管设置有发射极层，基极层和集电极层。 发射极层形成在衬底之上，并且是包括第一氮化物半导体的n型导电层。 基极层形成在发射极层上，是包含第二氮化物半导体的p型导体。 集电极层形成在基极层上并且包括第三氮化物半导体。 形成集电体层，基极层和发射极层，使得到基板表面的晶体生长方向平行于[000-1]的基板方向。 第三氮化物半导体含有InycAlxcGa1-xc-ycN（0·xc·1,0,0·yc·1,0,0cc·yc·1）。 第三氮化物半导体中的表面侧的a轴长度比基板侧的a轴长短。

公开(公告)号：US08674407B2

公开(公告)日：2014-03-18

申请号：US12919640

申请日：2009-03-12

申请人： Yuji Ando ,  Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

发明人： Yuji Ando ,  Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

IPC分类号： H01L29/66

CPC分类号： H01L29/7783 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/7785

摘要： The present invention provides a semiconductor device having such a structure formed by sequentially laminating a lower barrier layer composed of lattice-relaxed AlxGa1-xN (0≦x≦1), a channel layer composed of InyGa1-yN (0≦y≦1) with compressive strain and a contact layer composed of AlzGa1-zN (0≦z≦1), wherein a two-dimensional electron gas is produced in the vicinity of an interface of said InyGa1-yN channel layer with said AlzGa1-zN contact layer; a gate electrode is formed so as to be embedded in the recessed portion with intervention of an insulating film, which recessed portion is formed by removing a part of said AlzGa1-zN contact layer by etching it away until said InyGa1-yN channel layer is exposed; and, ohmic electrodes are formed on the AlzGa1-zN contact layer. Thus, the semiconductor device has superior uniformity and reproducibility of the threshold voltage while maintaining a low gate leakage current, and is also applicable to the enhancement mode type.

摘要翻译： 本发明提供一种具有这样的结构的半导体器件，该半导体器件通过依次层叠由晶格弛豫的Al x Ga 1-x N（0 @ x @ 1）构成的下阻挡层，由InyGa1-yN（0 @ y @ 1） 具有压应变和由Al z Ga 1-z N（0 @ z @ 1）组成的接触层，其中在所述In y Ga 1-y N沟道层与所述Al z Ga 1-z N接触层的界面附近产生二维电子气; 通过介入绝缘膜形成嵌入在凹陷部分中的栅电极，该凹陷部分通过蚀刻除去所述AlzGa1-zN接触层的一部分而形成，直到所述In y Ga 1-y N沟道层暴露 ; 并且在AlzGa1-zN接触层上形成欧姆电极。 因此，半导体器件在保持低栅极漏电流的同时具有优异的阈值电压的均匀性和再现性，并且也适用于增强型。

公开(公告)号：US20110241075A1

公开(公告)日：2011-10-06

申请号：US13124872

申请日：2009-10-16

申请人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Kazuki Ota

发明人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Kazuki Ota

IPC分类号： H01L29/737

CPC分类号： H01L29/7371 ,  H01L29/045 ,  H01L29/2003

摘要： A bipolar transistor includes: a substrate; a collector and a base layer with a p-conductive-type, an emitter layer with an n-conductive-type. The collector layer is formed above the substrate and includes a first nitride semiconductor. The base layer with the p-conductive-type is formed on the collector layer and includes a second nit ride semiconductor. The emitter layer with the n-conductive-type is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed so that crystal growing directions with respect to a surface of the substrate are in parallel to a [0001] direction of the substrate. The first nitride semiconductor includes: InycAlxcGa1-xc-ycN (0≦xc≦1, 0≦yc≦1, 0

摘要翻译： 双极晶体管包括：基板; 具有p导电型的集电极和基极层，具有n导电型的发射极层。 集电极层形成在衬底上方并且包括第一氮化物半导体。 具有p型导电型的基底层形成在集电极层上，并且包括第二耐磨半导体。 具有n导电型的发射极层形成在基极层上并且包括第三氮化物半导体。 形成集电体层，基极层和发射极层，使得相对于基板的表面的晶体生长方向与基板的[0001]方向平行。 第一氮化物半导体包括：InycAlxcGa1-xc-ycN（0＆nlE; xc＆nlE; 1,0＆amp; nlE; yc＆nlE; 1,0

公开(公告)号：US08772785B2

公开(公告)日：2014-07-08

申请号：US13141448

申请日：2009-11-26

申请人： Yasuhiro Okamoto ,  Hironobu Miyamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

发明人： Yasuhiro Okamoto ,  Hironobu Miyamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

IPC分类号： H01L29/15

CPC分类号： H01L29/872 ,  H01L29/08 ,  H01L29/2003 ,  H01L29/475

摘要： A semiconductor device includes semiconductor layers, an anode electrode, and a cathode electrode. The semiconductor layers include a composition change layer, the anode electrode is electrically connected to one of principal surfaces of the composition change layer through a formation of a Schottky junction between the anode electrode and a part of the semiconductor layers, the cathode electrode is electrically connected to the other of the principal surfaces of the composition change layer through a formation of a junction between the cathode electrode and another part of the semiconductor layers, the anode electrode and the cathode electrode are capable of applying a voltage to the composition change layer in a direction perpendicular to the principal surface.

摘要翻译： 半导体器件包括半导体层，阳极电极和阴极电极。 半导体层包括组成变化层，阳极电极通过在阳极电极和一部分半导体层之间形成肖特基结而与组合物变化层的主表面电连接，阴极电连接 通过在阴极电极和另一部分半导体层之间形成接合而形成组合物变化层的另一个主表面，阳极电极和阴极电极能够向组合物变化层施加电压 方向垂直于主表面。

公开(公告)号：US20110297954A1

公开(公告)日：2011-12-08

申请号：US13141448

申请日：2009-11-26

申请人： Yasuhiro Okamoto ,  Hironobu Miyamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

发明人： Yasuhiro Okamoto ,  Hironobu Miyamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

IPC分类号： H01L29/20 ,  H01L21/329

CPC分类号： H01L29/872 ,  H01L29/08 ,  H01L29/2003 ,  H01L29/475

摘要： [Problem to be Solved] Provided is a semiconductor device in which the trade-off between the pressure resistance and the on-state resistance is improved and the performance is improved.[Solution] The semiconductor device 1 of the present invention comprises semiconductor layers 20 to 23, an anode electrode 12, and a cathode electrode 13, wherein the semiconductor layers include a composition change layer 23, the anode electrode 12 is electrically connected to one of principal surfaces of the composition change layer through a formation of a Schottky junction between the anode electrode 12 and a part of the semiconductor layers, the cathode electrode 13 is electrically connected to the other of the principal surfaces of the composition change layer through a formation of a junction between the cathode electrode 13 and another part of the semiconductor layers, the anode electrode 12 and the cathode electrode 13 are capable of applying a voltage to the composition change layer 23 in a direction perpendicular to the principal surface, andthe composition change layer 23 has composition that changes from a cathode electrode 13 side toward an anode electrode 12 side in the direction perpendicular to the principal surface of the composition change layer, has a negative polarization charge that is generated due to the composition that changes, and contains a donor impurity.

摘要翻译： [待解决的问题]提供了一种半导体器件，其中改善了耐压性和通态电阻之间的折衷，并提高了性能。 [解决方案]本发明的半导体器件1包括半导体层20至23，阳极电极12和阴极电极13，其中半导体层包括组成变化层23，阳极电极12电连接到 通过在阳极12和半导体层的一部分之间形成肖特基结，组成变化层的主表面通过形成阴极电极13而与组合物改变层的另一个主表面电连接 阴极电极13和半导体层的另一部分之间的接合点，阳极电极12和阴极电极13能够在垂直于主表面的方向上向组合物变化层23施加电压，并且组成变化层 23具有从阴极电极13侧向阳极电极12侧变化的组成 具有垂直于组成变化层的主表面的方向具有由于组成变化而产生并且包含施主杂质的负极化电荷。

公开(公告)号：US20110006346A1

公开(公告)日：2011-01-13

申请号：US12919640

申请日：2009-03-12

申请人： Yuji Ando ,  Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

发明人： Yuji Ando ,  Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

IPC分类号： H01L29/737

CPC分类号： H01L29/7783 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/7785

摘要： The present invention provides a semiconductor device that has high electron mobility while reducing a gate leakage current, and superior uniformity and reproducibility of the threshold voltage, and is also applicable to the enhancement mode type. The semiconductor device according to the present invention is a semiconductor device having such a structure formed by sequentially laminating a lower barrier layer composed of lattice-relaxed AlxGa1-xN (0≦x≦1), a channel layer composed of InyGa1-yN (0≦y≦1) with compressive strain and a contact layer composed of AlzGa1-zN (0≦z≦1), wherein a two-dimensional electron gas is produced in the vicinity of an interface of said InyGa1-yN channel layer with said AlzGa1-zN contact layer; a gate electrode is formed so as to be embedded in the recessed portion with intervention of an insulating film, which recessed portion is formed by removing a part of said AlzGa1-zN contact layer by etching it away until said InyGa1-yN channel layer is exposed; and, ohmic electrodes are formed on the AlzGa1-zN contact layer. Thus, there is provided a semiconductor device that has superior uniformity and reproducibility of the threshold voltage while maintaining a low gate leakage current and high electron mobility, and thereby, is capable of operation in enhancement mode.

摘要翻译： 本发明提供了一种在降低栅极漏电流的同时具有高电子迁移率并具有优异的阈值电压的均匀性和再现性的半导体器件，并且也适用于增强型。 根据本发明的半导体器件是具有这样的结构的半导体器件，该半导体器件通过顺序地层叠由晶格弛豫的Al x Ga 1-x N（0＆lt; n 1; x＆n 1; 1）构成的下阻挡层，由InyGa1-yN（0＆ ; y＆nlE; 1）具有压应变和由AlzGa1-zN（0＆amp; nlE; z＆nlE; 1）组成的接触层，其中在所述In y Ga 1-y N沟道层的界面附近产生二维电子气体与所述AlzGa1 -zN接触层 通过介入绝缘膜形成嵌入在凹陷部分中的栅电极，该凹陷部分通过蚀刻除去所述AlzGa1-zN接触层的一部分而形成，直到所述In y Ga 1-y N沟道层暴露 ; 并且在AlzGa1-zN接触层上形成欧姆电极。 因此，提供了具有优异的阈值电压的均匀性和再现性的半导体器件，同时保持低栅极漏电流和高电子迁移率，从而能够在增强模式下操作。

公开(公告)号：US08981434B2

公开(公告)日：2015-03-17

申请号：US13393002

申请日：2010-06-23

申请人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

发明人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

IPC分类号： H01L29/76 ,  H01L29/812 ,  H01L29/201 ,  H01L29/78 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L29/8122 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7809 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/8128

摘要： Provided is a semiconductor device in which the trade-off between the withstand voltage and the on-resistance is improved and the performance is increased. A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The second n-type semiconductor layer 23 has composition that changes from the drain electrode 13 side toward the source electrode 12 side in the direction perpendicular to the plane of the substrate 1 and contains donor impurity.

摘要翻译： 提供一种半导体器件，其中耐压和导通电阻之间的折衷被提高并且性能提高。 半导体器件包括衬底1，第一n型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'，其中第一n型半导体层 型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'依次层叠在基板1的上侧。 漏电极13与第一n型半导体层21'欧姆接触，源电极12与第三n型半导体层25'欧姆接触。 栅电极14被布置成填充从第三n型半导体层25'延伸到第二n型半导体层23的待填充的开口部分，并且栅电极14与上表面 第二n型半导体层23，p型半导体层24的侧表面和第三n型半导体层25'的侧表面。 第二n型半导体层23具有从垂直于基板1的平面的方向从漏电极13侧向源电极12侧变化的成分，并且含有施主杂质。

公开(公告)号：US08674409B2

公开(公告)日：2014-03-18

申请号：US13141449

申请日：2009-12-25

申请人： Takashi Inoue ,  Hironobu Miyamoto ,  Kazuki Ota ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Yuji Ando

发明人： Takashi Inoue ,  Hironobu Miyamoto ,  Kazuki Ota ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Yuji Ando

IPC分类号： H01L29/66

CPC分类号： H01L29/7787 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/66462

摘要： A heterojunction filed effect transistor with a low access resistance, a low on resistance, and the like, a method for producing a heterojunction filed effect transistor and an electron device are provided. In the heterojunction field effect transistor, an electron transit layer 11 formed of a III-nitride semiconductor is formed on a substrate 10, an electron supply layer 12 formed of a III-nitride semiconductor forms a heterojunction with an upper surface of the electron transit layer 11, a gate electrode 14, a source electrode 15A, and a drain electrode 15B are arranged on the electron supply layer 12, n-type conductive layer regions 13A and 13B each extended from an upper part of the electron transit layer 11 to an upper surface of the electron supply layer 12 are provided in at least a part below the source electrode 15A and a part below the drain electrode 15B, and an n-type impurity concentration at a heterojunction interface of an electron transit layer 11 part of each of the n-type conductive layer regions 13A and 13B with the electron supply layer 12 is 1×1020 cm−3 or more.

摘要翻译： 提供具有低访问阻抗，低导通电阻等的异质结场效应晶体管，提供了异质结场效应晶体管和电子器件的制造方法。 在异质结场效应晶体管中，在衬底10上形成由III族氮化物半导体形成的电子迁移层11，由III族氮化物半导体形成的电子供给层12与电子迁移层的上表面形成异质结 如图11所示，在电子供给层12上配置有栅电极14，源电极15A和漏电极15B，从电子渡越层11的上部延伸到上部的n型导电层区域13A，13B 电子供给层12的表面设置在源电极15A的下方以及漏电极15B的下方的至少一部分以及电子迁移层11的异质界面的n型杂质浓度 具有电子供给层12的n型导电层区域13A，13B为1×1020cm-3以上。

公开(公告)号：US20120199889A1

公开(公告)日：2012-08-09

申请号：US13393002

申请日：2010-06-23

申请人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

发明人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

IPC分类号： H01L29/78

CPC分类号： H01L29/8122 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7809 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/8128

摘要： Provided is a semiconductor device in which the trade-off between the withstand voltage and the on-resistance is improved and the performance is increased.A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The second n-type semiconductor layer 23 has composition that changes from the drain electrode 13 side toward the source electrode 12 side in the direction perpendicular to the plane of the substrate 1 and contains donor impurity.

摘要翻译： 提供一种半导体器件，其中耐压和导通电阻之间的折衷被提高并且性能提高。 半导体器件包括衬底1，第一n型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'，其中第一n型半导体层 型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'依次层叠在基板1的上侧。 漏电极13与第一n型半导体层21'欧姆接触，源电极12与第三n型半导体层25'欧姆接触。 栅电极14被布置成填充从第三n型半导体层25'延伸到第二n型半导体层23的待填充的开口部分，并且栅电极14与上表面 第二n型半导体层23，p型半导体层24的侧表面和第三n型半导体层25'的侧表面。 第二n型半导体层23具有从垂直于基板1的平面的方向从漏电极13侧向源电极12侧变化的成分，并且含有施主杂质。