公开(公告)号：US5227681A

公开(公告)日：1993-07-13

申请号：US715772

申请日：1991-06-14

申请人： Mikio Koyama ,  Hiroshi Tanimoto

发明人： Mikio Koyama ,  Hiroshi Tanimoto

IPC分类号： G06G7/184 ,  H03H11/04

CPC分类号： G06G7/184 ,  H03H11/0433 ,  H03H11/045

摘要： An integration circuit includes a differential amplifier constituted by at least two bipolar transistors serving as amplifying elements, a capacitor connected, as a load, to the differential amplifier, and a field-effect transistor having source and drain electrodes connected between the emitter electrodes of the two bipolar transistors. A control voltage is applied to the gate electrode of the field-effect transistor.

公开(公告)号：US07619473B2

公开(公告)日：2009-11-17

申请号：US11812378

申请日：2007-06-18

申请人： Hiroshi Tanimoto ,  Masayuki Katakura

发明人： Hiroshi Tanimoto ,  Masayuki Katakura

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/45475 ,  H03F3/45659 ,  H03F3/45748 ,  H03F3/45757 ,  H03F3/45973 ,  H03F3/45982 ,  H03F2200/513 ,  H03F2203/45082 ,  H03F2203/45088 ,  H03F2203/45134 ,  H03F2203/45212 ,  H03F2203/45526 ,  H03F2203/45644

摘要： A fully-differential amplifier able to operate at a low power supply voltage and provided with a common-mode signal suppression function is disclosed. This fully-differential amplifier is provided with a first fully-differential amplifier configured by a single-stage configuration inverting amplifier and canceling out the common-mode signal of the input side by a feedforward means and a second fully-differential amplifier configured by a single-stage configuration inverting amplifier and canceling out the common-mode signal of the output side by a feedback means, the output of the first fully-differential amplifier being connected to the input of the second fully-differential amplifier.

摘要翻译： 公开了能够在低电源电压下工作并提供共模信号抑制功能的全差分放大器。 该全差分放大器配备有由单级配置反相放大器配置的第一全差分放大器，并且由前馈装置消除输入侧的共模信号，并且由单个配置反相放大器配置的第二全差分放大器 级配置反相放大器，并通过反馈装置消除输出侧的共模信号，第一全差分放大器的输出连接到第二全差分放大器的输入端。

公开(公告)号：US5943637A

公开(公告)日：1999-08-24

申请号：US773129

申请日：1996-12-26

申请人： Makiko Okumura ,  Hiroshi Tanimoto

发明人： Makiko Okumura ,  Hiroshi Tanimoto

IPC分类号： G06F17/50 ,  G06F9/06

CPC分类号： G06F17/5036

摘要： A noise analyzing apparatus includes an input unit for inputting a structure of an autonomous system, parameter values and analysis conditions, a periodic steady-state solution calculating unit for calculating a periodic steady-state solution of the autonomous system, a noise source adding unit for adding a noise source to a periodic linear time-variant system obtained by linearizing the autonomous system around the periodic steady-state solution, a time-variant transfer function calculating unit for calculating, for each noise source, a time-variant transfer function of the periodic linear time-variant system to which noise sources are added, a reflected component calculating unit for adding power of a time-variant transfer function reflected to a frequency to be observed, and an output unit for outputting as a result of analysis relating to noise based on results of calculations by the above-described calculating units.

摘要翻译： 一种噪声分析装置，包括输入自动系统的结构的输入单元，参数值和分析条件，用于计算自主系统的周期性稳态解的周期性稳态解决计算单元，噪声源加法单元， 将周期性线性时变系统的周期性线性时变系统加到周期性的稳态解周围的自动系统中，对每个噪声源计算每个噪声源的时变传递函数的时变传递函数计算单元， 添加噪声源的周期性线性时变系统，用于将反映到待观察频率的时变传递函数的功率相加的反射分量计算单元，以及作为噪声分析结果输出的输出单元 基于上述计算单元的计算结果。

公开(公告)号：US5471171A

公开(公告)日：1995-11-28

申请号：US45537

申请日：1993-04-09

申请人： Tetsuro Itakura ,  Hiroshi Tanimoto

发明人： Tetsuro Itakura ,  Hiroshi Tanimoto

IPC分类号： H03F1/02 ,  H03F3/45

CPC分类号： H03F3/3022 ,  H03F1/0244 ,  H03F1/0261 ,  H03F3/301 ,  H03F2203/30048 ,  H03F2203/30121 ,  H03F2203/45008 ,  H03F2203/45014 ,  H03F2203/45466

摘要： An amplifier device capable of performing an efficient amplifying operation with a low power consumption includes an amplifier circuit at least having an input amplifier stage which amplifies a level change of an input signal to output an amplified current, and an output stage which outputs the amplified current as a driving output to a capacitive load; a primary bias circuit for ordinarily supplying a constant and main bias current to the amplifier circuit; a determination element for determining a change condition of the level change of the input signal, which is supplied from the input amplifier stage, so as to generate a control signal corresponding to said change condition; and a driving capability increase element as a secondary bias circuit for increasing a bias current in order to increase the driving output supplied to the capacitive load when the control signal is input.

摘要翻译： 能够以低功耗进行高效放大运算的放大器装置，具有至少具有放大输入信号的电平变化以输出放大电流的输入放大级的放大电路，以及输出放大电流的输出级 作为电容性负载的驱动输出; 用于通常向放大器电路提供恒定和主偏置电流的初级偏置电路; 确定元件，用于确定从输入放大器级提供的输入信号的电平变化的变化状态，以产生对应于所述变化条件的控制信号; 以及作为用于增加偏置电流的次级偏置电路的驱动能力增加元件，以便当输入控制信号时增加提供给电容性负载的驱动输出。

公开(公告)号：US5399992A

公开(公告)日：1995-03-21

申请号：US152887

申请日：1993-11-16

申请人： Tetsuro Itakura ,  Hiroshi Tanimoto

发明人： Tetsuro Itakura ,  Hiroshi Tanimoto

IPC分类号： H03F3/45 ,  H03F1/02 ,  H03K17/04 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/094

CPC分类号： H03F1/0244 ,  H03F1/0261 ,  H03F3/301 ,  H03F3/3022 ,  H03F2203/30048 ,  H03F2203/30121 ,  H03F2203/45008 ,  H03F2203/45014 ,  H03F2203/45466

摘要： An amplifier device includes: a current amplifier element for amplifying an output current delivered to a capacitive load, such as, for example, a liquid crystal panel in dependency upon changes of the voltage of an input signal; an element for determining the state of changes in the input signal; and a control element for controlling the current amplifier element depending upon the state of changes in the input signal determined by the determination element in order to improve the output driving capability for the load. This amplifier device is applicable to an amplifier in a narrow sense and a buffer circuit in accordance with the mode of amplification. The former may include the configuration in which a second bias circuit for adding a bias current when the driving capability is required to be enhanced is provided in addition to an elementary bias circuit, and the configuration in which a first output drive element and the second output drive element and a plurality of output drive elements succeeding thereto are provided for additionally carrying out switching between incremental output currents. The latter may be classified into two types depending upon whether or not the potential difference element provided on the output side of the buffer circuit to detect a potential difference between the input and the output to add the output current when the the potential difference thus detected is above the threshold level.

摘要翻译： 放大器装置包括：电流放大器元件，用于根据输入信号的电压变化放大输出到电容性负载的输出电流，例如液晶面板; 用于确定输入信号的变化状态的元件; 以及控制元件，用于根据由确定元件确定的输入信号的变化状态来控制电流放大器元件，以便提高负载的输出驱动能力。 该放大器装置适用于狭义上的放大器和根据放大模式的缓冲电路。 前者可以包括除了基本偏置电路之外还提供了在需要增强驱动能力时用于增加偏置电流的第二偏置电路的配置，以及其中第一输出驱动元件和第二输出 驱动元件和其后的多个输出驱动元件被设置用于附加地执行增量输出电流之间的切换。 后者可以分为两种类型，这取决于当这样检测的电位差时，缓冲电路的输出侧的电位差元件是否检测输入和输出之间的电位差以增加输出电流 高于阈值水平。

公开(公告)号：US5373533A

公开(公告)日：1994-12-13

申请号：US839165

申请日：1992-02-21

申请人： Mikio Hayashihara ,  Hiroshi Tsurumi ,  Hiroshi Tanimoto

发明人： Mikio Hayashihara ,  Hiroshi Tsurumi ,  Hiroshi Tanimoto

IPC分类号： H04L27/14 ,  H04L27/152

CPC分类号： H04L27/1525

摘要： An FSK signal receiving device is constituted by a first phase shifting circuit for applying a first phase shift to a first reception base band signal of first and second reception base band signals having orthogonal phases to generate a third base band signal, and generating a fourth base band signal having a phase orthogonal to the phase of the third base band signal, a second phase shifting circuit for applying the first phase shift to the second base band signal to generate a fifth reception base band signal, and a logical gate circuit for performing an exclusive OR operation on the third and fourth base band signals to obtain a first output signal, on the third and fifth base signals to obtain a second output signal, and on the first and second output signals to generate a detection signal.

摘要翻译： FSK信号接收装置由用于对具有正交相位的第一和第二接收基带信号的第一接收基带信号施加第一相移以产生第三基带信号的第一相移电路构成，并且产生第四基带 具有与第三基带信号的相位正交的相位的频带信号;第二移相电路，用于将第一相移施加到第二基带信号以产生第五接收基带信号，以及逻辑门电路，用于执行 在第三和第四基带信号上进行异或运算以在第三和第五基本信号上获得第一输出信号以获得第二输出信号，并且在第一和第二输出信号上产生检测信号。

公开(公告)号：US5079515A

公开(公告)日：1992-01-07

申请号：US531798

申请日：1990-05-31

申请人： Hiroshi Tanimoto

发明人： Hiroshi Tanimoto

IPC分类号： H03F1/32 ,  H03F3/45

CPC分类号： H03F1/3211 ,  H03F3/45071

摘要： Disclosed is a linearized differential amplifier, comprising connecting input terminals and output terminals of the differential pairs respectively in parallel; arranging N sets of differential pairs (where N is an integer of at least 3); an offset voltage generating circuit for supplying different and equivalent offset voltages to the respective differential pairs; a circuit for weighting these output currents; and a circuit for adding the output currents. Particularly, the offset voltage generating circuit and the weighting circuit carry out equivalent weighting of the offset voltages and the output currents so that the change of the differential output current corresponding to the change of the differential input voltage shows an equal ripple characteristic. Moreover, to give equivalent offset voltages to the respective differential pairs, a linearized differential amplifier where emitter areas in respective differential pairs are different is disclosed. In this case, the ratio of emitter areas is 1:7.872983 and 1:1 when N is 3, and 1:13.40261 and 1:2.030215 when N is 4.

公开(公告)号：US4904952A

公开(公告)日：1990-02-27

申请号：US254242

申请日：1988-10-06

申请人： Hiroshi Tanimoto

发明人： Hiroshi Tanimoto

IPC分类号： H03F1/32 ,  H03F3/45

CPC分类号： H03F1/3211 ,  H03F3/45103

摘要： A differential amplifier capable of achieving a large amplification, a wide frequency range, a high common mode rejection ratio, and a wide dynamic range simultaneously includes a device to produce negative resistance connected to output terminals. The differential amplifier also includes level shift circuits to generate additional voltages.

公开(公告)号：US4743872A

公开(公告)日：1988-05-10

申请号：US909161

申请日：1986-09-19

申请人： Hiroshi Tanimoto

发明人： Hiroshi Tanimoto

IPC分类号： H03K17/687 ,  H03H19/00 ,  H03H7/01

CPC分类号： H03H19/004

摘要： A switched capacitor circuit comprises first and second switches connected in series between an input terminal and a first fixed potential terminal and third and fourth switches connected in series between an output terminal and the first fixed potential terminal. The group of the first and fourth switches and the group of the second and third switches are alternately rendered conducting and nonconducting. Two serial capacitors are connected between the junction of the first and second switches and the junction of the third and fourth switches and one parallel capacitor is connected between the junction of the two serially connected capacitors and the first fixed potential. The common junction of the three capacitors is connected to a second fixed potential terminal through a highly resistive element.

摘要翻译： 开关电容器电路包括串联连接在输入端子和第一固定电位端子之间的第一和第二开关以及串联连接在输出端子和第一固定电位端子之间的第三和第四开关。 第一和第四开关的组和第二和第三开关的组交替地导通和不导通。 两个串联电容器连接在第一和第二开关的连接点与第三和第四开关的结点之间，并且一个并联电容器连接在两个串联电容器的结和第一固定电位之间。 三个电容器的公共端通过高电阻元件连接到第二固定电位端子。

公开(公告)号：US06714604B1

公开(公告)日：2004-03-30

申请号：US09604838

申请日：2000-06-27

申请人： Hiroshi Tsurumi ,  Hiroshi Yoshida ,  Shoji Otaka ,  Hiroshi Tanimoto

发明人： Hiroshi Tsurumi ,  Hiroshi Yoshida ,  Shoji Otaka ,  Hiroshi Tanimoto

IPC分类号： H04B126

CPC分类号： H04B1/0014 ,  H04B1/0007 ,  H04B1/0039 ,  H04B1/28

摘要： An orthogonal demodulating section converts the frequency of received signals to the lower range in batch after rejecting an image band thereof by an RF filter. An image rejecting section rejects the image band of the orthogonally converted output. It allows an enough image rejecting degree to be obtained. An A/D converter section converts the whole range into a digital signal and an orthogonal demodulating section demodulates a desirable channel by means of digital processing. Then, a channel selecting section selects and outputs the desirable channel. It then allows wide-bands to be received in batch, flexible processing to be achieved by the digital processing and an enough image rejecting degree to be obtained.

摘要翻译： 正交解调部在通过RF滤波器拒绝其图像频带之后，将接收信号的频率分批转换为较低范围。 图像拒绝部分拒绝正交转换输出的图像带。 它允许获得足够的图像拒绝度。 A / D转换器部分将整个范围转换为数字信号，并且正交解调部分通过数字处理解调期望的信道。 然后，频道选择部分选择并输出所需频道。 然后允许批量接收宽带，通过数字处理实现灵活处理，并获得足够的图像拒绝度。