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    Semiconductor memory device having redundant memory cells
    11.
    发明授权
    Semiconductor memory device having redundant memory cells 失效
    具有冗余存储单元的半导体存储器件

    公开(公告)号：US5450361A

    公开(公告)日：1995-09-12

    申请号：US197410

    申请日：1994-02-16

    申请人： Hiroshi Iwahashi ,  Hiroto Nakai ,  Kazuhisa Kanazawa ,  Isao Sato

    发明人： Hiroshi Iwahashi ,  Hiroto Nakai ,  Kazuhisa Kanazawa ,  Isao Sato

    IPC分类号： G11C7/14 ,  G11C16/28 ,  G11C16/32 ,  G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/842 ,  G11C16/28 ,  G11C16/32 ,  G11C7/14

    摘要： There is disclosed a semiconductor memory device comprising memory cells (M11 to Mmn) for storing binary data, and first reference cells (DM11 to DMm1) and second reference cells (DM12 to DMm2) corresponding to respective two storage states of the memory cell, to make comparisons between the storage state of the memory cell and the storage states of the both reference cells at first and second sense amplifiers (1, 2) to compare outputs from the both sense amplifiers at the third sense amplifier (3) to thereby detect storage data of the memory cell. Thus, there can be provided a high speed memory device which has a less number of memory cells and of a high integration structure, and which has a little possibility of an erroneous operation in reading.

    摘要翻译： 公开了一种半导体存储器件，包括用于存储二进制数据的存储器单元（M11至Mmn）和对应于存储器单元的两个存储状态的第一参考单元（DM11至DMm1）和第二参考单元（DM12至DMm2），以及 比较存储单元的存储状态和第一和第二读出放大器（1,2）处的两个参考单元的存储状态，以比较来自第三读出放大器（3）的两个读出放大器的输出，从而检测存储 存储单元的数据。 因此，可以提供一种具有较少数量的存储器单元和高集成结构的高速存储器件，并且其读取中错误操作的可能性很小。

    Semiconductor memory device
    12.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5321655A

    公开(公告)日：1994-06-14

    申请号：US111050

    申请日：1993-08-24

    申请人： Hiroshi Iwahashi ,  Hiroto Nakai ,  Kazuhisa Kanazawa ,  Isao Sato

    发明人： Hiroshi Iwahashi ,  Hiroto Nakai ,  Kazuhisa Kanazawa ,  Isao Sato

    IPC分类号： G11C7/14 ,  G11C16/28 ,  G11C16/32 ,  G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/842 ,  G11C16/28 ,  G11C16/32 ,  G11C7/14

    摘要： There is disclosed a semiconductor memory device comprising memory cells (M11 to Mnn) for storing binary data, and first reference cells (DM11 to Dm1) and second reference cells (DM12 to DMm2) corresponding to respective two storage states of the memory cell, to make comparisons between the storage state of the memory cell and the storage states of the both reference cells at first and second sense amplifiers (1, 2) to compare outputs from the both sense amplifiers at the third sense amplifier (3) to thereby detect storage data of the memory cell. Thus, there can be provided a high speed memory device which has a less number of memory cells and of a high integration structure, and which has a little possibility of an erroneous operation in reading.

    摘要翻译： 公开了一种半导体存储器件，包括用于存储二进制数据的存储器单元（M11至Mnn）和与存储器单元的相应两个存储状态对应的第一参考单元（DM11至Dm1）和第二参考单元（DM12至DMm2），以及 比较存储单元的存储状态和第一和第二读出放大器（1,2）处的两个参考单元的存储状态，以比较来自第三读出放大器（3）的两个读出放大器的输出，从而检测存储 存储单元的数据。 因此，可以提供一种具有较少数量的存储器单元和高集成结构的高速存储器件，并且其读取中错误操作的可能性很小。

    Block erasable nonvolatile memory device
    20.
    发明授权
    Block erasable nonvolatile memory device 失效
    块可擦除非易失性存储器件

    公开(公告)号：US5371702A

    公开(公告)日：1994-12-06

    申请号：US27489

    申请日：1993-03-05

    申请人： Hiroto Nakai ,  Hideo Kato ,  Kaoru Tokushige ,  Masamichi Asano ,  Kazuhisa Kanazawa ,  Toshio Yamamura

    发明人： Hiroto Nakai ,  Hideo Kato ,  Kaoru Tokushige ,  Masamichi Asano ,  Kazuhisa Kanazawa ,  Toshio Yamamura

    IPC分类号： G11C16/16 ,  G11C11/34 ,  G11C7/00

    CPC分类号： G11C16/16

    摘要： In response to a plurality of address signal input from the outside in sequence, an erase information inputting section controls an erase information holding section corresponding to the batch erase block to be erased so as to hold an erase information data. By repeating this operation in sequence, the erase information data are stored in the erase information holding sections corresponding to the plural batch erase blocks to be erased. Successively, on the basis of the erase information data stored in the erase information holding sections, block erasing sections are activated to erase all the nonvolatile memory cells of each of the corresponding blocks where the erase information data are held. As a result, the erasure operation is achieved for all the batch erase blocks corresponding to the erase information holding sections in each of which the erase information data is held, so that a plurality of batch erase blocks can be erased simulataneously, thus reducing the erasure time, as compared with the prior art memory device.

    摘要翻译： 响应于从外部依次输入的多个地址信号，擦除信息输入部分控制与待擦除的批量擦除块相对应的擦除信息保持部分，以便保存擦除信息数据。 通过依次重复该操作，擦除信息数据被存储在与要擦除的多批擦除块相对应的擦除信息保持部分中。 接着，基于存储在擦除信息保持部中的擦除信息数据，块消除部分被激活，以擦除保持擦除信息数据的每个相应块的所有非易失性存储器单元。 结果，对于与保持擦除信息数据的擦除信息保持部分相对应的所有批量擦除块实现擦除操作，使得可以同时擦除多个批量擦除块，从而减少擦除 与现有技术的存储器件相比。