Aqueous emulsion composition and adherent composition

    公开(公告)号:US07026369B2

    公开(公告)日:2006-04-11

    申请号:US10199036

    申请日:2002-07-22

    IPC分类号: C08F2/50 C08F2/16

    摘要: To provide an aqueous emulsion composition which has high adhesion strength for a wide variety of materials including molded products and affords sufficient wettability even for the object to be adhesive bonded of low surface polarity so that it can develop sufficient adhesiveness and whose emulsion is stable so satisfactorily as to provide good mechanical stability and storage stability, and to provide an adherent composition comprising the aqueous emulsion composition, at least ethylene-vinyl acetate copolymer or modified resin thereof, photo polymerization initiator, and unsaturated ethylenic monomer are mixed and dissolved or dispersed, to prepare oil drop component, followed by emulsifying the oil drop component in water by using a surface-active agent, whereby an aqueous emulsion composition, in which micelles each encapsulating at least the ethylene-vinyl acetate copolymer or modified resin thereof, the photo polymerization initiator and unsaturated ethylenic monomer are dispersed in water, is prepared.

    Epitaxial wafer
    12.
    发明授权
    Epitaxial wafer 有权
    外延晶圆

    公开(公告)号:US06818197B2

    公开(公告)日:2004-11-16

    申请号:US10390941

    申请日:2003-03-18

    IPC分类号: C01B3326

    摘要: A wafer of the invention is a silicon wafer of 0.02 &OHgr;cm or less in resistivity for deposition of an epitaxial layer, and the number of crystal originated particles (COP) and the number of interstitial-type large dislocation loops (L/D) are respectively 0 to 10 per wafer. A wafer of the invention is an epitaxial wafer having an epitaxial layer being 0.1 &OHgr;cm or more in resistivity and 0.5 to 5 &mgr;m in thickness formed on this wafer by means of a CVD method. A wafer of the invention is OSF-free and hardly makes traces of COP and L/D appear on the surface of an epitaxial layer when the epitaxial layer is formed. By heat treatment in a semiconductor device manufacturing process after the epitaxial layer is formed, BMDs occur uniformly and highly in density in the wafer and a uniform IG effect can be obtained in the wafer.

    摘要翻译: 本发明的晶片是用于沉积外延层的电阻率为0.02Ω·cm以下的硅晶片,并且晶体起始粒子(COP)的数量和间隙型大位错环(L / D)的数量分别为 每片晶片为0〜10。 本发明的晶片是通过CVD方法在该晶片上形成的外延层的外延层的电阻率为0.1μΩ·m以上,厚度为0.5〜5μm的外延片。 当形成外延层时,本发明的晶片是无OSF的,并且几乎不产生COP和L / D的痕迹出现在外延层的表面上。 通过在形成外延层之后的半导体器件制造工艺中的热处理,BMD在晶片中的密度均匀且高度地发生,并且可以在晶片中获得均匀的IG效应。

    Method for evaluating the quality of a semiconductor substrate
    13.
    发明授权
    Method for evaluating the quality of a semiconductor substrate 有权
    用于评估半导体衬底的质量的方法

    公开(公告)号:US06693286B2

    公开(公告)日:2004-02-17

    申请号:US10299148

    申请日:2002-11-19

    IPC分类号: G01N2164

    CPC分类号: G01N21/6489 G01N21/6408

    摘要: A first chopper between a laser device and a semiconductor substrate chops an excitation light at a specific frequency, and a second chopper between the first chopper and the semiconductor substrate chops the excitation light at a variable frequency higher than the first chopper. A photoluminescence light emitted by the semiconductor substrate when the semiconductor substrate is intermittently irradiated with the excitation light is introduced into a monochromator. A controller obtains the decay time constant T of the photoluminescence light from variation of the average intensity of the photoluminescence light when gradually increasing the chopping frequency of the excitation light by controlling the second chopper, and computes the life time &tgr; of the semiconductor substrate from an expression “&tgr;=T/C”, where C is a constant. An object of the invention is to accurately evaluate impurities, defects and the like in a semiconductor substrate by obtaining quantitatively the life time of the semiconductor substrate having a long life time.

    摘要翻译: 激光装置与半导体基板之间的第一斩波器以特定频率切断激励光,第一斩波器与半导体基板之间的第二斩波器以比第一斩波器高的可变频率对激发光进行斩波。 当半导体衬底间歇地用激发光照射时,由半导体衬底发射的光致发光被引入到单色器中。 控制器通过控制第二斩波器逐渐增加激发光的斩波频率,从光致发光光的平均强度的变化中获得光致发光光的衰减时间常数T,并计算半导体衬底的寿命τ 表达式“tau = T / C”,其中C是常数。 本发明的目的是通过定量地获得具有长寿命的半导体衬底的寿命来准确地评估半导体衬底中的杂质,缺陷等。

    Gas barrier polyurethane resin
    14.
    发明授权
    Gas barrier polyurethane resin 有权
    防气聚氨酯树脂

    公开(公告)号:US06569533B1

    公开(公告)日:2003-05-27

    申请号:US09619639

    申请日:2000-07-19

    IPC分类号: B32B2706

    摘要: A polyurethane resin having a total concentration of the urethane group and the urea group of not less than 15% by weight is prepared by reacting a diisocyanate component (e.g., an aromatic diisocyanate) with a diol component (e.g., a C2-8alkylene glycol). The repeating unit of the polyurethane resin may contain a constitutive unit of an aromatic or alicyclic compound. The polyurethane resin may be shaped into a film for use as a gas barrier film. The film may be a gas barrier composite film composed of a base film layer and a resin layer at least comprising the polyurethane resin. The present invention provides a polyurethane resin excellent in gas barrier properties against water vapor, oxygen, aromatics, and others, and a film containing the same.

    摘要翻译: 通过使二异氰酸酯成分(例如芳香族二异氰酸酯)与二醇成分(例如C 2-8亚烷基二醇)反应,制备氨基甲酸酯基和脲基的总浓度为15重量%以上的聚氨酯树脂, 。 聚氨酯树脂的重复单元可以含有芳族或脂环族化合物的组成单元。 聚氨酯树脂可以成形为用作阻气膜的膜。 该膜可以是由至少包含聚氨酯树脂的基膜层和树脂层构成的阻气性复合膜。 本发明提供了对水蒸气,氧气,芳烃等的阻气性优异的聚氨酯树脂和含有该聚氨酯树脂的膜。

    Heat treatment jig and heat treatment method for silicon wafer
    16.
    发明授权
    Heat treatment jig and heat treatment method for silicon wafer 有权
    硅片热处理夹具及热处理方法

    公开(公告)号:US08026182B2

    公开(公告)日:2011-09-27

    申请号:US12339118

    申请日:2008-12-19

    IPC分类号: H01L21/302

    摘要: In this heat treatment jig and method for silicon wafers, a silicon wafer is heat-treated while being mounted on support projections provided on three support arms, having an intervening spacing, protruding from a support frame towards the center. At that time, all the support projections under the silicon wafer are positioned on a same circle within a region where a radial distance from the center is defined by 85 to 99.5% of the wafer radius, and the support arms form an angle of 120° with each other about the center. With this jig and method, free depth of a dislocation generated from a pin position can be controlled deeper than a device formation region, and a widest slip-free region where the surface is free from slip dislocation is obtained.

    摘要翻译: 在这种用于硅晶片的热处理夹具和方法中,将硅晶片安装在设置在三个支撑臂上的支撑突起上进行热处理,其具有从支撑框架向中心突出的中间间隔。 此时,硅晶片下面的所有支撑突起都位于与中心的径向距离限定晶片半径的85至99.5%的区域内的相同的圆上,并且支撑臂形成120°的角度 彼此围绕中心。 利用这种夹具和方法,可以将从销位置产生的位错的自由深度控制得比装置形成区域更深,并且获得表面没有滑移位错的最宽的无滑动区域。

    Production method for silicon wafers and silicon wafer
    17.
    发明授权
    Production method for silicon wafers and silicon wafer 有权
    硅晶片和硅晶片的生产方法

    公开(公告)号:US07670965B2

    公开(公告)日:2010-03-02

    申请号:US11053440

    申请日:2005-02-09

    CPC分类号: H01L21/3225

    摘要: A silicon wafer is thermal-annealed in an atmosphere to form new vacancies therein by thermal annealing and the atmosphere in the thermal annealing contains a nitride gas having a lower decomposition temperature than a decomposable temperature of N2 so that the thermal annealing is carried out at a lower temperature or for a short time to suppress generation of slip and to provide satisfactory surface roughness.

    摘要翻译: 将硅晶片在大气中热退火以通过热退火形成新的空位,并且热退火中的气氛含有分解温度低于N2的可分解温度的氮化物气体,使得热退火在 较低的温度或短时间以抑制滑移的产生并提供令人满意的表面粗糙度。

    Heat treatment jig and heat treatment method for silicon wafer
    18.
    发明授权
    Heat treatment jig and heat treatment method for silicon wafer 有权
    硅片热处理夹具及热处理方法

    公开(公告)号:US07481888B2

    公开(公告)日:2009-01-27

    申请号:US10551695

    申请日:2004-03-30

    IPC分类号: C23C16/00

    摘要: In this heat treatment jig and method for silicon wafers, a silicon wafer is heat-treated while being mounted on support projections provided on three support arms, having an intervening spacing, protruding from a support frame towards the center. At that time, all the support projections under the silicon wafer are positioned on a same circle within a region where a radial distance from the center is defined by 85 to 99.5% of the wafer radius, and the support arms form an angle of 120° with each other about the center. With this jig and method, free depth of a dislocation generated from a pin position can be controlled deeper than a device formation region, and a widest slip-free region where the surface is free from slip dislocation is obtained.

    摘要翻译: 在这种用于硅晶片的热处理夹具和方法中,将硅晶片安装在设置在三个支撑臂上的支撑突起上进行热处理,其具有从支撑框架向中心突出的中间间隔。 此时,硅晶片下面的所有支撑突起都位于与中心的径向距离限定晶片半径的85至99.5%的区域内的相同的圆上,并且支撑臂形成120°的角度 彼此围绕中心。 利用这种夹具和方法,可以将从销位置产生的位错的自由深度控制得比装置形成区域更深,并且获得表面没有滑移位错的最宽的无滑动区域。

    Silicon wafer heat treatment jig, and silicon wafer heat treatment method
    19.
    发明申请
    Silicon wafer heat treatment jig, and silicon wafer heat treatment method 有权
    硅晶片热处理夹具,硅晶片热处理方法

    公开(公告)号:US20060208434A1

    公开(公告)日:2006-09-21

    申请号:US10551695

    申请日:2004-03-30

    IPC分类号: B23B31/28 B29C71/00

    摘要: In this heat treatment jig and method for silicon wafers, a silicon wafer is heat-treated while being mounted on support projections provided on three support arms, having an intervening spacing, protruding from a support frame towards the center. At that time, all the support projections under the silicon wafer are positioned on a same circle within a region where a radial distance from the center is defined by 85 to 99.5% of the wafer radius, and the support arms form an angle of 120° with each other about the center. With this jig and method, free depth of a dislocation generated from a pin position can be controlled deeper than a device formation region, and a widest slip-free region where the surface is free from slip dislocation is obtained.

    摘要翻译: 在这种用于硅晶片的热处理夹具和方法中,将硅晶片安装在设置在三个支撑臂上的支撑突起上进行热处理,其具有从支撑框架向中心突出的中间间隔。 此时,硅晶片下面的所有支撑突起都位于与中心的径向距离限定晶片半径的85至99.5%的区域内的相同的圆上,并且支撑臂形成120°的角度 彼此围绕中心。 利用这种夹具和方法,可以将从销位置产生的位错的自由深度控制得比装置形成区域更深,并且获得表面没有滑移位错的最宽的无滑动区域。

    Semiconductor device
    20.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号:US06384633B1

    公开(公告)日:2002-05-07

    申请号:US09812823

    申请日:2001-03-21

    IPC分类号: H03K190175

    摘要: A semiconductor device is provided. The semiconductor device includes a repeater performing buffering operation at some midpoint in a multiplex bus over which an address and data are transmitted by a time division method. The repeater includes a part which transmits only an address when the address does not indicate a data transmission destination which is located ahead of the repeater.

    摘要翻译: 提供半导体器件。 半导体器件包括中继器,在多路复用总线的某个中点进行缓冲操作,通过时分方法发送地址和数据。 中继器包括当地址不指示位于中继器之前的数据传输目的地时仅发送地址的部分。