公开(公告)号：US06841925B2

公开(公告)日：2005-01-11

申请号：US10323079

申请日：2002-12-19

Applicant: Song Geun Lee ,  Ho Jin Cho ,  Kwang Yun Choi

Inventor： Song Geun Lee ,  Ho Jin Cho ,  Kwang Yun Choi

IPC: H01J29/76 ,  H01J29/82 ,  H01J29/70 ,  H04N5/655

CPC classification number: H01J29/76 ,  H01J29/826

Abstract: Disclosed is a deflection yoke comprising: a fastening band of a ring shape assembled on an outer periphery of a neck portion in a coil separator by a fixing manner, provided for being extended and contracted; a pair of flanges bent and extended from both ends of the fastening band, on which a through hole is formed; a yoke clamp for generating fastening force by tightening of a bolt for passing through a pair of through holes, then being tightened by a nut; a bending portion projected on an outer side along the periphery of the fastening band, whose object contact plane for coming in contact with an outer periphery of the neck portion is divided into at least two or more.

Abstract translation: 本发明公开了一种偏转线圈，其特征在于，包括：通过固定方式组装在线圈分离器的颈部的外周上的环状的紧固带，用于延伸和收缩; 从形成有通孔的紧固带的两端弯曲并延伸的一对凸缘; 用于通过拧紧用于穿过一对通孔的螺栓产生紧固力的轭夹，然后由螺母紧固; 沿着紧固带的外周突出的外侧的弯曲部分，其与颈部的外周接触的物体接触面被划分为至少两个以上。

公开(公告)号：US20120098132A1

公开(公告)日：2012-04-26

申请号：US13279546

申请日：2011-10-24

Applicant: Cheol Hwan PARK ,  Ho Jin Cho ,  Dong Kyun Lee

Inventor： Cheol Hwan PARK ,  Ho Jin Cho ,  Dong Kyun Lee

IPC: H01L29/43 ,  H01L21/28

CPC classification number: H01L28/75

Abstract: A semiconductor device with a stable structure having high capacitance by changing the pillar type storage node structure and a method of manufacturing the same are provided. The method includes forming a sacrificial layer on a semiconductor substrate including a storage node contact plug, etching the sacrificial layer to form a region exposing the storage node contact plug, forming a first conductive material within an inner side of the region, burying a second conductive material within the region in which the first conductive material is formed, and removing the sacrificial layer to form a pillar type storage node.

Abstract translation: 提供了通过改变柱型存储节点结构具有高电容的稳定结构的半导体器件及其制造方法。 该方法包括在包括存储节点接触插塞的半导体衬底上形成牺牲层，蚀刻牺牲层以形成露出存储节点接触插塞的区域，在该区域内侧形成第一导电材料，将第二导电 在其中形成第一导电材料的区域内的材料，以及去除牺牲层以形成柱状存储节点。

公开(公告)号：US08148764B2

公开(公告)日：2012-04-03

申请号：US13185873

申请日：2011-07-19

Applicant: Cheol Hwan Park ,  Ho Jin Cho ,  Dong Kyun Lee

Inventor： Cheol Hwan Park ,  Ho Jin Cho ,  Dong Kyun Lee

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10894

Abstract: A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conducive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.

Abstract translation: 提出了具有高方位圆柱形电容器的半导体器件及其制造方法。 高档圆柱型电容器是一种稳定的结构，不容易造成保护环中的掩体缺陷和损失。 半导体器件包括圆柱形电容器结构，存储节点氧化物，保护环孔，导电层和封盖氧化物。 单元区域中的圆柱型电容器结构包括圆筒形下电极，电介质和上电极。 存储节点氧化物位于半导体衬底上的周边区域中。 导电层涂覆保护环孔。 在与半导体基板上的单元区域相邻的周边区域的边界处的保护环孔。 覆盖氧化物部分地填充导电层的一部分。 间隙填充膜填充在导电层的其余部分。

公开(公告)号：US07723183B2

公开(公告)日：2010-05-25

申请号：US12499248

申请日：2009-07-08

Applicant: Ho Jin Cho ,  Cheol Hwan Park ,  Jae Soo Kim ,  Dong Kyun Lee

Inventor： Ho Jin Cho ,  Cheol Hwan Park ,  Jae Soo Kim ,  Dong Kyun Lee

IPC: H01L21/02

CPC classification number: H01L28/65 ,  H01L27/10852 ,  H01L28/91

Abstract: A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper portion of the storage node contact plug. A tapering layer is deposited over the mold insulation layer including the hole. The tapering layer and the buffer oxide layer are etched back so that the tapering layer is remained only at the upper end portion of the etched hole. A metal storage node layer formed on the etched hole over the remaining tapering layer. The mold insulation layer and the remaining tapering layer are removed to form a cylindrical storage node having a tapered upper end. A dielectric layer and a plate node are formed over the storage node.

Abstract translation: 通过在具有存储节点接触插塞的半导体衬底上形成缓冲氧化物层，蚀刻停止层和模具绝缘层来制造电容器。 蚀刻模具绝缘层和蚀刻停止层，以在存储节点接触插塞的上部形成孔。 在包括孔的模具绝缘层上沉积渐缩层。 锥形层和缓冲氧化物层被回蚀刻，使得锥形层仅保留在蚀刻孔的上端部。 在剩余的锥形层上形成在蚀刻孔上的金属储存节点层。 去除模具绝缘层和剩余的锥形层以形成具有锥形上端的圆柱形存储节点。 在存储节点上形成介电层和板状节点。

公开(公告)号：US07208419B2

公开(公告)日：2007-04-24

申请号：US10738397

申请日：2003-12-17

Applicant: Seung Woo Jin ,  Bong Soo Kim ,  Ho Jin Cho

Inventor： Seung Woo Jin ,  Bong Soo Kim ,  Ho Jin Cho

IPC: H01L21/302

CPC classification number: H01L21/823418 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823468

Abstract: The present invention relates to a method for fabricating a semiconductor device. The method comprises the steps of: forming a gate line on a semiconductor substrate; forming a buffer layer and a spacer nitride film on the entire surface of the substrate including the gate line; selectively etching the buffer layer and the spacer nitride film in such a manner that they remain on both sides of the gate line; performing an ion implantation process using the remaining buffer layer and spacer nitride film as a barrier film to form junction regions in the semiconductor substrate at both sides of the gate line; forming an interlayer insulating film on the entire upper portion of the resulting substrate; selectively removing the interlayer insulating film to form contact holes exposing the upper surface of the junction regions; and forming contact plugs in the contact holes.

Abstract translation: 本发明涉及半导体器件的制造方法。 该方法包括以下步骤：在半导体衬底上形成栅极线; 在包括栅极线的基板的整个表面上形成缓冲层和间隔氮化物膜; 选择性地蚀刻缓冲层和间隔氮化物膜，使得它们保留在栅极线的两侧; 使用剩余缓冲层和间隔氮化物膜作为阻挡膜进行离子注入工艺，以在栅极线的两侧在半导体衬底中形成结区域; 在所得基板的整个上部形成层间绝缘膜; 选择性地去除层间绝缘膜以形成暴露接合区域的上表面的接触孔; 并在接触孔中形成接触塞。

公开(公告)号：US06800567B2

公开(公告)日：2004-10-05

申请号：US10226028

申请日：2002-08-22

Applicant: Ho Jin Cho

Inventor： Ho Jin Cho

IPC: H01L2131

CPC classification number: H01L21/02271 ,  H01L21/02197 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/31691 ,  H01L21/318

Abstract: A method for forming a polyatomic layer with a mixed deposition method consisting of an atomic layer deposition method (ALD) and a chemical vapor deposition method. The mixed deposition method can be adopted to form a polyatomic high dielectric layer, such as BST or STO. Accordingly, it is possible to form a polyatomic high dielectric layer having a uniform composition distribution, and thereby also having a high dielectric characteristic and a low leakage current characteristic.

Abstract translation: 一种由原子层沉积法（ALD）和化学气相沉积法组成的混合沉积法形成多原子层的方法。 可以采用混合沉积法形成诸如BST或STO的多原子高介电层。 因此，可以形成具有均匀组成分布的多原子高电介质层，从而也具有高介电特性和低漏电流特性。

公开(公告)号：US6054332A

公开(公告)日：2000-04-25

申请号：US414236

申请日：1999-10-07

Applicant: Ho Jin Cho

Inventor： Ho Jin Cho

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/00

CPC classification number: H01L28/55 ,  H01L28/60 ,  H01L28/75

Abstract: The present invention provides a method for fabricating a capacitor of a semiconductor memory device to improve the characteristic of step coverage during depositing upper electrode, and simultaneously to prevent impurities remained between upper electrode and high dielectric layer.The method for fabricating capacitor of a semiconductor memory device comprises the steps of: forming an intermetal insulating layer having a contact hole for exposing a junction region on a semiconductor substrate provided with the junction region; forming a contact plug within the contact hole; forming a barrier layer on the contact plug and on the adjoining intermetal insulating layer; forming a lower electrode so as to surround the barrier layer; forming a high dielectric layer on the intermetal insulating layer formed on the lower electrode; forming an upper electrode on the high dielectric layer according to the MOCVD method; and crystallizing the lower electrode, the high dielectric layer and the upper electrode, wherein in the step of forming the upper electrode, a step of supplying precursors used for forming the upper electrode for a selected time, and a step of interrupting the supply of precursors for a selected time are repeated at least one time.

Abstract translation: 本发明提供了一种用于制造半导体存储器件的电容器的方法，以改善在沉积上电极期间阶梯覆盖的特性，同时防止上电极和高电介质层之间残留的杂质。 制造半导体存储器件的电容器的方法包括以下步骤：形成具有接触孔的金属间绝缘层，用于暴露具有接合区域的半导体衬底上的接合区域; 在所述接触孔内形成接触塞; 在接触插塞和相邻的金属间绝缘层上形成阻挡层; 形成下部电极以包围阻挡层; 在形成在下电极上的金属间绝缘层上形成高介电层; 根据MOCVD方法在高电介质层上形成上电极; 以及使下电极，高电介质层和上电极结晶，其中在形成上电极的步骤中，提供用于选择时间形成上电极的前体的步骤，以及中断前体供给步骤 至少一次重复选定的时间。

公开(公告)号：US07906419B2

公开(公告)日：2011-03-15

申请号：US12275332

申请日：2008-11-21

Applicant: Jae Soo Kim ,  Cheol Hwan Park ,  Ho Jin Cho

Inventor： Jae Soo Kim ,  Cheol Hwan Park ,  Ho Jin Cho

IPC: H01L21/3205

CPC classification number: H01L21/268 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66621

Abstract: A laser annealing method for manufacturing a semiconductor device is presented. The method includes at least two forming steps and one annealing step. The first forming steps includes forming gates on a semiconductor substrate. The second forming step includes forming an insulation layer on the semiconductor substrate and on the gates. The annealing step includes annealing the insulation layer using electromagnetic radiation emitted from a laser.

Abstract translation: 提出了一种用于制造半导体器件的激光退火方法。 该方法包括至少两个形成步骤和一个退火步骤。 第一形成步骤包括在半导体衬底上形成栅极。 第二形成步骤包括在半导体衬底上和栅极上形成绝缘层。 退火步骤包括使用从激光发射的电磁辐射对绝缘层进行退火。

公开(公告)号：US20080070398A1

公开(公告)日：2008-03-20

申请号：US11758512

申请日：2007-06-05

Applicant: Dong Su Park ,  Ho Jin Cho ,  Keum Bum Lee ,  Su Jin Chae ,  Cheol-Hwan Park

Inventor： Dong Su Park ,  Ho Jin Cho ,  Keum Bum Lee ,  Su Jin Chae ,  Cheol-Hwan Park

IPC: H01L23/525

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is a method of fabricating a semiconductor device having a metal fuse. The method includes forming a plate electrode on a semiconductor substrate, forming an interlayer insulating layer on the plate electrode, forming a barrier metal layer containing either silicon or aluminum, a first metal layer and an antireflection layer containing either silicon or aluminum sequentially from bottom to top on the interlayer insulating layer. The method also includes patterning the antireflection layer, the first metal layer, and the barrier metal layer to form a first metal interconnection. The method also includes forming a fuse with the same material and structure as those of the first metal interconnection while forming the first metal interconnection. The method further includes forming an inter-metal dielectric layer on the first metal interconnection and the fuse, forming a second metal interconnection on the inter-metal dielectric layer, forming a passivation layer on the second metal interconnection, and forming a fuse box in the passivation layer.

Abstract translation: 这里公开了一种制造具有金属保险丝的半导体器件的方法。 该方法包括在半导体衬底上形成平板电极，在平板电极上形成层间绝缘层，从底部依次形成含有硅或铝的阻挡金属层，第一金属层和含有硅或铝的抗反射层， 顶层在层间绝缘层上。 该方法还包括图案化抗反射层，第一金属层和阻挡金属层以形成第一金属互连。 该方法还包括形成具有与第一金属互连相同的材料和结构的熔丝，同时形成第一金属互连。 该方法还包括在第一金属互连和熔丝上形成金属间电介质层，在金属间绝缘层上形成第二金属互连，在第二金属互连上形成钝化层，并在第 钝化层。

公开(公告)号：US07300852B2

公开(公告)日：2007-11-27

申请号：US11089122

申请日：2005-03-24

Applicant: Ho Jin Cho ,  Jun Soo Chang ,  Eun A. Lee ,  Su Jin Chae ,  Young Dae Kim

Inventor： Ho Jin Cho ,  Jun Soo Chang ,  Eun A. Lee ,  Su Jin Chae ,  Young Dae Kim

IPC: H01L21/20

CPC classification number: H01L21/02312 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/3144 ,  H01L28/60

Abstract: A method for manufacturing a capacitor of a semiconductor element including: forming a bottom electrode of the capacitor on a semiconductor substrate; performing rapid thermal nitrification (RTN) on the upper surface of the bottom electrode; performing a thermal process on the obtained structure having the bottom electrode in a furnace under a nitride atmosphere to eliminate stress generated by the RTN; forming Al2O3 and HfO2 dielectric films on the nitrified bottom electrode; and forming a plate electrode of the capacitor on the Al2O3 and HfO2 dielectric films. The thermal process is performed after the RTN performed on the surface of the bottom electrode, so that stress, generated from the RTN, is alleviated, thereby allowing the capacitor to obtain a high capacitance and lowering leakage current.

Abstract translation: 一种制造半导体元件的电容器的方法，包括：在半导体衬底上形成电容器的底部电极; 在底电极的上表面进行快速热硝化（RTN）; 对所获得的在氮化物气氛下的炉中具有底部电极的结构进行热处理以消除由RTN产生的应力; 在硝化的底部电极上形成Al 2 O 3 N 3和HfO 2 N 2电介质膜; 以及在Al 2 O 3和HfO 2 N 2电介质膜上形成电容器的平板电极。 在底电极表面进行RTN之后进行热处理，从而可以减轻由RTN产生的应力，从而使电容器获得高电容，降低漏电流。