利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

59 条记录 (耗时 0.029 秒)

    Semiconductor device with drain-end drift diminution
    11.
    发明授权
    Semiconductor device with drain-end drift diminution 有权
    漏极端漂移的半导体器件减少

    公开(公告)号：US08853780B2

    公开(公告)日：2014-10-07

    申请号：US13465761

    申请日：2012-05-07

    申请人： Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

    发明人： Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

    IPC分类号： H01L29/66

    CPC分类号： H01L29/063 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

    摘要： A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate, a channel region in the semiconductor substrate between the source and drain regions through which charge carriers flow during operation from the source region to the drain region, and a drift region in the semiconductor substrate, on which the drain region is disposed, and through which the charge carriers drift under an electric field arising from application of a bias voltage between the source and drain regions. A PN junction along the drift region includes a first section at the drain region and a second section not at the drain region. The drift region has a lateral profile that varies such that the first section of the PN junction is shallower than the second section of the PN junction.

    摘要翻译： 一种器件包括半导体衬底，半导体衬底中的源极和漏极区域，在源极和漏极区域之间的半导体衬底中的沟道区域，电荷载体在从源极区域到漏极区域的工作期间流过该沟道区域，以及漂移区域 其上设置有漏极区的半导体衬底，并且电荷载流子在源极和漏极区域之间施加偏压产生的电场下漂移。 沿着漂移区域的PN结包括在漏极区域处的第一部分和不在漏极区域的第二部分。 漂移区域具有变化的横向轮廓，使得PN结的第一部分比PN结的第二部分浅。

    NONVOLATILE MEMORY BITCELL
    12.
    发明申请
    NONVOLATILE MEMORY BITCELL 审中-公开
    非易失性存储器BITCELL

    公开(公告)号：US20140209988A1

    公开(公告)日：2014-07-31

    申请号：US13756248

    申请日：2013-01-31

    申请人： Xin Lin ,  Hongning Yang ,  Zhihong Zhang ,  Jiang-Kai Zuo

    发明人： Xin Lin ,  Hongning Yang ,  Zhihong Zhang ,  Jiang-Kai Zuo

    IPC分类号： H01L29/66 ,  H01L27/088

    CPC分类号： H01L29/66825 ,  H01L27/11558 ,  H01L29/7881

    摘要： A multiple time programmable nonvolatile memory device having a single polysilicon memory cell includes a select transistor and a bitcell transistor. The bitcell transistor has asymmetrically configured source, drain, and channel regions including asymmetrically configured source-body and drain-body junctions. Compared with the drain-body junction, the impurity concentration gradient of the source-body junction is more gradual, which may significantly improve program disturb immunity. The bitcell transistor gate may be connected to an electrode of a coupling capacitor, but may be otherwise floating or Ohmically isolated. The floating gate of the bitcell is protected by a dielectric layer for potentially improved data retention.

    摘要翻译： 具有单个多晶硅存储单元的多时间可编程非易失性存储器件包括选择晶体管和位单元晶体管。 位单元晶体管具有不对称配置的源极，漏极和沟道区域，包括不对称配置的源极体和漏极 - 体部结。 与漏 - 体结相比，源 - 体结的杂质浓度梯度更为平缓，可以显着提高程序的干扰免疫力。 位单元晶体管栅极可以连接到耦合电容器的电极，但是可以以浮置或欧姆隔离的方式。 位单元的浮动栅极由介电层保护，以便潜在地改善数据保持。

    SEMICONDUCTOR DEVICE WITH ENHANCED 3D RESURF
    13.
    发明申请
    SEMICONDUCTOR DEVICE WITH ENHANCED 3D RESURF 有权
    具有增强3D修复功能的半导体器件

    公开(公告)号：US20140203358A1

    公开(公告)日：2014-07-24

    申请号：US13748076

    申请日：2013-01-23

    申请人： Hongning Yang ,  Xin Lin ,  Zhihong Zhang ,  Jiang-Kai Zuo

    发明人： Hongning Yang ,  Xin Lin ,  Zhihong Zhang ,  Jiang-Kai Zuo

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/66681 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/7835

    摘要： A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region.

    摘要翻译： 一种器件包括半导体衬底，半导体衬底中的源极和漏极区域以及沿着第一横向尺寸彼此间隔开的半导体衬底中的漂移区域，并且在施加偏置电压之前电荷载体在操作期间漂移 源极和漏极区域。 漂移区域沿着漂移区域和漏极区域之间的界面在第二横向维度上具有缺口掺杂剂分布。

    DIE EDGE SEALING STRUCTURES AND RELATED FABRICATION METHODS
    15.
    发明申请
    DIE EDGE SEALING STRUCTURES AND RELATED FABRICATION METHODS 有权
    DIE边缘密封结构和相关制造方法

    公开(公告)号：US20150056751A1

    公开(公告)日：2015-02-26

    申请号：US14505842

    申请日：2014-10-03

    申请人： Zhihong Zhang ,  Hongning Yang ,  Jiang-Kai Zuo

    发明人： Zhihong Zhang ,  Hongning Yang ,  Jiang-Kai Zuo

    IPC分类号： H01L23/00 ,  H01L21/78

    CPC分类号： H01L23/562 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region. In one or more embodiments, the edge sealing structure includes a conductive material that contacts a handle layer of semiconductor material, a crackstop structure is formed overlying the sealing structure, wherein the crackstop structure and the edge sealing structure provide an electrical connection between the handle layer and an active layer of semiconductor material that overlies a buried layer of dielectric material on the handle layer.

    摘要翻译： 提供电子器件的模具结构和相关的制造方法。 示例性的管芯结构包括半导体衬底的切割部分，其包括其上制造有一个或多个半导体器件的器件区域和在该半导体衬底内限定器件区域的边缘密封结构。 在一个或多个实施例中，边缘密封结构包括接触半导体材料的手柄层的导电材料，形成在密封结构上方的裂缝结构，其中裂缝结构和边缘密封结构在手柄层之间提供电连接 以及覆盖在手柄层上的介电材料的掩埋层的半导体材料的有源层。

    Semiconductor device and related fabrication methods
    16.
    发明授权
    Semiconductor device and related fabrication methods 有权
    半导体器件及相关制造方法

    公开(公告)号：US09070576B2

    公开(公告)日：2015-06-30

    申请号：US13606797

    申请日：2012-09-07

    申请人： Hongning Yang ,  Zhihong Zhang ,  Jiang-Kai Zuo

    发明人： Hongning Yang ,  Zhihong Zhang ,  Jiang-Kai Zuo

    IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/45 ,  H01L29/49 ,  H01L29/06 ,  H01L29/10

    CPC分类号： H01L29/0878 ,  H01L29/0653 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66689 ,  H01L29/7824

    摘要： Semiconductor device structures and related fabrication methods are provided. An exemplary method of fabricating a semiconductor device on a doped region of semiconductor material having a first conductivity type involves forming a first region having a second conductivity type within the doped region, forming a body region having the first conductivity type overlying the first region, and forming a drift region having the second conductivity type within the doped region, wherein at least a portion of the drift region abuts at least a portion of the first region. In one embodiment, the dopant concentration of the first region is less than the dopant concentration of the body region and different from the dopant concentration of the drift region.

    摘要翻译： 提供半导体器件结构和相关的制造方法。 在具有第一导电类型的半导体材料的掺杂区域上制造半导体器件的示例性方法包括在掺杂区域内形成具有第二导电类型的第一区域，形成覆盖第一区域的具有第一导电类型的体区，以及 在所述掺杂区域内形成具有所述第二导电类型的漂移区，其中所述漂移区的至少一部分邻接所述第一区的至少一部分。 在一个实施例中，第一区域的掺杂剂浓度小于体区的掺杂剂浓度，并且不同于漂移区的掺杂剂浓度。

    Die edge sealing structures and related fabrication methods
    18.
    发明授权
    Die edge sealing structures and related fabrication methods 有权
    模边密封结构及相关制造方法

    公开(公告)号：US09331025B2

    公开(公告)日：2016-05-03

    申请号：US14505842

    申请日：2014-10-03

    申请人： Zhihong Zhang ,  Hongning Yang ,  Jiang-Kai Zuo

    发明人： Zhihong Zhang ,  Hongning Yang ,  Jiang-Kai Zuo

    IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L21/78 ,  H01L23/31 ,  H01L23/58

    CPC分类号： H01L23/562 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region. In one or more embodiments, the edge sealing structure includes a conductive material that contacts a handle layer of semiconductor material, a crackstop structure is formed overlying the sealing structure, wherein the crackstop structure and the edge sealing structure provide an electrical connection between the handle layer and an active layer of semiconductor material that overlies a buried layer of dielectric material on the handle layer.

    摘要翻译： 提供电子器件的模具结构和相关的制造方法。 示例性的管芯结构包括半导体衬底的切割部分，其包括其上制造有一个或多个半导体器件的器件区域和在该半导体衬底内限定器件区域的边缘密封结构。 在一个或多个实施例中，边缘密封结构包括接触半导体材料的手柄层的导电材料，形成在密封结构上方的裂缝结构，其中裂缝结构和边缘密封结构在手柄层之间提供电连接 以及覆盖在手柄层上的介电材料的掩埋层的半导体材料的有源层。

    SEMICONDUCTOR DEVICE WITH COMPOSITE DRIFT REGION AND RELATED FABRICATION METHOD
    20.
    发明申请
    SEMICONDUCTOR DEVICE WITH COMPOSITE DRIFT REGION AND RELATED FABRICATION METHOD 有权
    具有复合缓冲区域的半导体器件及相关制造方法

    公开(公告)号：US20150333177A1

    公开(公告)日：2015-11-19

    申请号：US14279991

    申请日：2014-05-16

    申请人： Zhihong Zhang ,  Hongning Yang ,  Jiang-Kai Zuo

    发明人： Zhihong Zhang ,  Hongning Yang ,  Jiang-Kai Zuo

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/1045 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/36 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

    摘要： A device includes a semiconductor substrate, a body region in the semiconductor substrate having a first conductivity type and in which a channel is formed during operation, source and drain regions in the semiconductor substrate and having a second conductivity type, the source region being disposed on the body region, and a composite drift region in the semiconductor substrate, having the second conductivity type, and through which charge carriers from the source region drift to reach the drain region after passing through the channel. The composite drift region includes a first section adjacent the channel, a second section adjacent the drain region, and a third section disposed between the first and second sections. The first and second sections have a lower effective dopant concentration level than the third section.

    摘要翻译： 一种器件包括半导体衬底，半导体衬底中具有第一导电类型并且其中在工作期间形成沟道的主体区域，半导体衬底中的源极和漏极区域并具有第二导电类型，源极区域设置在 所述体区域和所述半导体衬底中的复合漂移区域具有第二导电类型，并且来自所述源极区域的电荷载流子通过所述复合漂移区域漂移以在通过所述沟道之后到达所述漏极区域。 复合漂移区域包括邻近通道的第一部分，与漏极区域相邻的第二部分，以及设置在第一和第二部分之间的第三部分。 第一和第二部分具有比第三部分更低的有效掺杂剂浓度水平。