公开(公告)号：US09306060B1

公开(公告)日：2016-04-05

申请号：US14548616

申请日：2014-11-20

申请人： Hongning Yang ,  Daniel J. Blomberg ,  Xin Lin ,  Zhihong Zhang ,  Jiang-Kai Zuo

发明人： Hongning Yang ,  Daniel J. Blomberg ,  Xin Lin ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

CPC分类号： H01L29/7823 ,  H01L21/26513 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66689 ,  H01L29/7835 ,  H01L29/78624

摘要： Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a body region of semiconductor material having a first conductivity type, a source region of semiconductor material having a second conductivity type within the body region, a junction isolation region of semiconductor material having the second conductivity type, a drain region of semiconductor material having the second conductivity type, and first and second drift regions of semiconductor material having the second conductivity type. The first drift region resides laterally between the drain region and the junction isolation region, the junction isolation region resides laterally between the first drift region and the second drift region, and the second drift region resides laterally between the body region and the junction isolation region.

摘要翻译： 提供半导体器件结构和相关的制造方法。 示例性的半导体器件结构包括具有第一导电类型的半导体材料的主体区域，在体区内具有第二导电类型的半导体材料的源极区域，具有第二导电类型的半导体材料的结隔离区域，漏极区域 具有第二导电类型的半导体材料以及具有第二导电类型的半导体材料的第一和第二漂移区。 第一漂移区域横向地位于漏极区域和结隔离区域之间，结隔离区域横向位于第一漂移区域和第二漂移区域之间，并且第二漂移区域横向居住在体区域和结隔离区域之间。

公开(公告)号：US09070576B2

公开(公告)日：2015-06-30

申请号：US13606797

申请日：2012-09-07

申请人： Hongning Yang ,  Zhihong Zhang ,  Jiang-Kai Zuo

发明人： Hongning Yang ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/45 ,  H01L29/49 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/0878 ,  H01L29/0653 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66689 ,  H01L29/7824

摘要： Semiconductor device structures and related fabrication methods are provided. An exemplary method of fabricating a semiconductor device on a doped region of semiconductor material having a first conductivity type involves forming a first region having a second conductivity type within the doped region, forming a body region having the first conductivity type overlying the first region, and forming a drift region having the second conductivity type within the doped region, wherein at least a portion of the drift region abuts at least a portion of the first region. In one embodiment, the dopant concentration of the first region is less than the dopant concentration of the body region and different from the dopant concentration of the drift region.

摘要翻译： 提供半导体器件结构和相关的制造方法。 在具有第一导电类型的半导体材料的掺杂区域上制造半导体器件的示例性方法包括在掺杂区域内形成具有第二导电类型的第一区域，形成覆盖第一区域的具有第一导电类型的体区，以及 在所述掺杂区域内形成具有所述第二导电类型的漂移区，其中所述漂移区的至少一部分邻接所述第一区的至少一部分。 在一个实施例中，第一区域的掺杂剂浓度小于体区的掺杂剂浓度，并且不同于漂移区的掺杂剂浓度。

公开(公告)号：US09041103B2

公开(公告)日：2015-05-26

申请号：US13781722

申请日：2013-02-28

申请人： Won Gi Min ,  Zhihong Zhang ,  Hongzhong Xu ,  Jiang-Kai Zuo

发明人： Won Gi Min ,  Zhihong Zhang ,  Hongzhong Xu ,  Jiang-Kai Zuo

IPC分类号： H01L29/772 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/7823 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall.

摘要翻译： 即使在身体和漂移区域电荷平衡不理想的情况下，即使在（i）在漏极附近提供插头或沉降片，即使通过仔细的电荷平衡，RESURF器件（例如LDMOS晶体管）中的击穿电压BVdss也能够降低导通电阻， 和/或（ii）将偏置Viso施加到耦合到器件掩埋层的周围横向掺杂隔离壁，和/或（iii）提供可变的 隔离墙和漂移区之间的电阻桥。 该桥可以是FET，其漏极耦合隔离壁和漂移区，并且其栅极接收控制电压Vc，或者其截面（X，Y，Z）影响其电阻和夹断的电阻器，以设置 通过隔离壁耦合到掩埋层的漏极电压的百分比。

公开(公告)号：US20130299939A1

公开(公告)日：2013-11-14

申请号：US13469386

申请日：2012-05-11

申请人： Yoba Amoah ,  John J. Ellis-Monaghan ,  Roger C. Kuo ,  Molly J. Leitch ,  Zhihong Zhang

发明人： Yoba Amoah ,  John J. Ellis-Monaghan ,  Roger C. Kuo ,  Molly J. Leitch ,  Zhihong Zhang

IPC分类号： H01L27/06 ,  H01L21/26

CPC分类号： H01L23/544 ,  H01L27/08 ,  H01L2223/5444 ,  H01L2223/5446 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

摘要： Various embodiments disclosed include methods of performing a double exposure process on a level of an integrated circuit (IC) chip to form an IC chip having an embedded electrically measurable identifier. In some cases, the method includes: exposing a level of an integrated circuit (IC) chip using a first mask orientation; subsequently exposing the level of the IC chip using a second mask orientation distinct from the first mask orientation; and developing the level of the IC chip to form an electrically measurable identifier on the IC chip.

摘要翻译： 公开的各种实施例包括在集成电路（IC）芯片的电平上执行双重曝光处理以形成具有嵌入的可电测量标识符的IC芯片的方法。 在一些情况下，该方法包括：使用第一掩模取向曝光集成电路（IC）芯片的电平; 随后使用与第一掩模取向不同的第二掩模取向暴露IC芯片的电平; 并且开发IC芯片的电平以在IC芯片上形成可电测量的标识符。

公开(公告)号：US20130265068A1

公开(公告)日：2013-10-10

申请号：US13443450

申请日：2012-04-10

申请人： Yoba Amoah ,  John J. Ellis-Monaghan ,  Roger C. Kuo ,  Molly J. Leitch ,  Zhihong Zhang

发明人： Yoba Amoah ,  John J. Ellis-Monaghan ,  Roger C. Kuo ,  Molly J. Leitch ,  Zhihong Zhang

IPC分类号： G01R31/3187

CPC分类号： G01R31/318511 ,  G01R31/2856 ,  G11C29/006 ,  G11C29/12 ,  G11C2029/1206

摘要： A method of testing a semiconductor wafer and a related structure. In various embodiments, a method includes: placing a probe on a first chip on the semiconductor wafer; testing a scribe line automatic built-in self-test (ABIST) for the first chip to search for a fault; progressively testing a subsequent scribe line ABIST for a subsequent chip on the semiconductor wafer in response to determining the ABIST for the first chip does not indicate the fault; moving the probe point to the subsequent chip and retesting the subsequent scribe line ABIST in response to determining the ABIST for the subsequent chip indicates a fault; and testing a further subsequent scribe line ABIST for a further subsequent chip on the semiconductor wafer in response to determining the retesting of the subsequent scribiline ABIST does not indicate a fault in the subsequent scribe line ABIST.

摘要翻译： 一种半导体晶片的测试方法及相关结构。 在各种实施例中，一种方法包括：将探针放置在半导体晶片上的第一芯片上; 测试划线自动内置自检（ABIST）为第一芯片寻找故障; 响应于确定第一芯片的ABIST而对半导体晶片上的后续芯片进行随后的划线ABIST的逐步测试不表示故障; 将探针点移动到随后的芯片，并且响应于确定随后芯片的ABIST指示故障，重新测试随后的划线ABIST; 以及响应于确定随后的scribiline的重新测试，测试另一后续划线ABIST用于半导体晶片上的另外的后续芯片，ABIST不指示后续划线ABIST中的故障。

公开(公告)号：US08491802B1

公开(公告)日：2013-07-23

申请号：US13042819

申请日：2011-03-08

申请人： Wei Gao ,  Dujiang Wan ,  Zhihong Zhang ,  Lijun Tong

发明人： Wei Gao ,  Dujiang Wan ,  Zhihong Zhang ,  Lijun Tong

IPC分类号： B29D11/00 ,  C03C15/00

CPC分类号： G11B5/6088 ,  G11B5/3133 ,  G11B2005/0021

摘要： A method of forming an energy assisted magnetic recording (EAMR) writer is disclosed. A structure comprising a bottom cladding layer and a near field transducer (NFT) is provided. A patterned sacrificial layer is formed over the structure. A top cladding layer is deposited over the patterned sacrificial layer and a remaining region of the structure not covered by the patterned sacrificial layer. A patterned resist is formed over the top cladding layer. A first etching operation is performed on the top cladding layer via the patterned resist, whereby a top cladding having a sloped region is formed. The patterned sacrificial layer provides an etch stop for the first etching operation.

摘要翻译： 公开了一种形成能量辅助磁记录（EAMR）写入器的方法。 提供包括底部包层和近场换能器（NFT）的结构。 在该结构上形成图案化的牺牲层。 顶部覆层沉积在图案化的牺牲层上，并且该结构的剩余区域未被图案化的牺牲层覆盖。 在顶部包层上形成图案化的抗蚀剂。 通过图案化的抗蚀剂在顶部包层上进行第一蚀刻操作，从而形成具有倾斜区域的顶部包层。 图案化的牺牲层为第一蚀刻操作提供蚀刻停止。

公开(公告)号：US08120402B2

公开(公告)日：2012-02-21

申请号：US12425366

申请日：2009-04-16

申请人： Zhihong Zhang ,  Xujiang Huang

发明人： Zhihong Zhang ,  Xujiang Huang

IPC分类号： H03K3/017 ,  H03K5/04 ,  H03K7/08

CPC分类号： H03K5/1565 ,  H02M3/156 ,  H03K3/017 ,  H03K7/08

摘要： A pulse width modulated (PWM) controller includes a triangle wave generation circuit generating a triangle wave signal to oscillate between an upper limit voltage and a lower limit voltage. The upper limit voltage and the lower limit voltage are adjustable in response to changes in the power supply voltage. A pulse generation circuit is coupled to the triangle wave generation circuit and a minimum duty cycle setting voltage, and is configured to generate a PWM pulse signal with a minimum duty cycle determined by the relative magnitude of the triangle wave signal and the minimum duty cycle reference voltage. In an embodiment, the minimum duty cycle is increased when the power supply voltage is lower than a predetermined reference voltage.

摘要翻译： 脉宽调制（PWM）控制器包括产生三角波信号的三角波产生电路，以在上限电压和下限电压之间振荡。 上限电压和下限电压可根据电源电压的变化而调节。 脉冲发生电路耦合到三角波产生电路和最小占空比设置电压，并且被配置为产生具有由三角波信号的相对幅度和最小占空比基准确定的最小占空比的PWM脉冲信号 电压。 在一个实施例中，当电源电压低于预定参考电压时，最小占空比增加。

公开(公告)号：US20110020242A1

公开(公告)日：2011-01-27

申请号：US12747815

申请日：2008-12-12

申请人： Gang Zheng ,  Zhihong Zhang ,  Ian Corbin ,  Juan Chen

发明人： Gang Zheng ,  Zhihong Zhang ,  Ian Corbin ,  Juan Chen

IPC分类号： A61K49/14 ,  C07K17/02 ,  A61K49/00 ,  A61K9/14 ,  A61P35/00

CPC分类号： A61K49/0082 ,  A61K47/6917 ,  A61K47/6919 ,  A61K49/0002 ,  A61K49/0032 ,  A61K49/0056 ,  B82Y5/00 ,  G01N33/54346 ,  G01N33/587 ,  G01N2800/00

摘要： The present invention provides a non-naturally occurring High-Density Lipoprotein-like peptide-phospholipid scaffold (“HPPS”) nanoparticle. More particularly, the invention provides a non-naturally occurring peptide-lipid nanoscaffold comprising: (a) at least one phospholipid; (b) at least one unsaturated lipid, preferably an unsaturated sterol ester, further preferably an unsaturated cholesterol ester, further preferably cholsteryl oleate; and (c) at least one peptide, the peptide comprising an amino acid sequence capable of forming at least one amphipathic a-helix; wherein the components a), b) and c) associate to form the peptide-phospholipid nanoscaffold. In embodiments of the present invention, a cell surface receptor ligand is incorporated into the HPPS. In one embodiment, the cell surface receptor ligand is covalently bonded to the peptide scaffold of the HPPS nanoparticles. In other embodiments, a cell surface receptor ligand is coupled to a lipid anchor and is displayed on the surface of the HPPS nanoparticles by incorporation of the lipid anchor into the phospholipids monolayer of the HPPS nanoparticle. The present invention also provides pharmaceutical formulations comprising HPPS nanoparticles and methods of making the HPPS nanoparticles.

摘要翻译： 本发明提供非天然存在的高密度脂蛋白样肽 - 磷脂支架（“HPPS”）纳米颗粒。 更具体地，本发明提供非天然存在的肽 - 脂质纳米支架，其包含：（a）至少一种磷脂; （b）至少一种不饱和脂质，优选不饱和甾醇酯，更优选不饱和胆固醇酯，更优选油酸胆甾醇酯; 和（c）至少一种肽，所述肽包含能够形成至少一种两亲性α-螺旋的氨基酸序列; 其中组分a），b）和c）缔合形成肽 - 磷脂纳米支架。 在本发明的实施方案中，将细胞表面受体配体掺入HPPS中。 在一个实施方案中，细胞表面受体配体共价键合到HPPS纳米颗粒的肽支架上。 在其它实施方案中，将细胞表面受体配体偶联到脂质锚定物上，并通过将脂质锚点掺入HPPS纳米颗粒的磷脂单层中而显示在HPPS纳米颗粒的表面上。 本发明还提供了包含HPPS纳米颗粒的药物制剂和制备HPPS纳米颗粒的方法。

公开(公告)号：US07603700B2

公开(公告)日：2009-10-13

申请号：US11023649

申请日：2004-12-29

申请人： Yan Cheng ,  Zhihong Zhang

发明人： Yan Cheng ,  Zhihong Zhang

IPC分类号： G06F7/04 ,  H04L9/32

CPC分类号： H04L63/08 ,  G06F21/41 ,  H04L9/3271 ,  H04L63/0428 ,  H04L63/18

摘要： Techniques are provided for improving security in a single-sign-on context by providing, to a user's client system, two linked authentication credentials in separate logical communication sessions and requiring that both credentials be presented to a host system. Only after presentation of both credentials is the user authenticated and permitted to access applications on the host system.

摘要翻译： 提供技术用于通过在单独的逻辑通信会话中向用户的客户端系统提供两个链接的认证凭证并且要求将这两个凭证提供给主机系统来提高单点登录上下文中的安全性。 只有在显示两个凭据之后，用户才能通过身份验证并允许访问主机系统上的应用程序。

公开(公告)号：US09666671B2

公开(公告)日：2017-05-30

申请号：US14279991

申请日：2014-05-16

申请人： Zhihong Zhang ,  Hongning Yang ,  Jiang-Kai Zuo

发明人： Zhihong Zhang ,  Hongning Yang ,  Jiang-Kai Zuo

IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/36 ,  H01L29/06 ,  H01L29/08 ,  H01L21/265

CPC分类号： H01L29/1045 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/36 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A device includes a semiconductor substrate, a body region in the semiconductor substrate having a first conductivity type and in which a channel is formed during operation, source and drain regions in the semiconductor substrate and having a second conductivity type, the source region being disposed on the body region, and a composite drift region in the semiconductor substrate, having the second conductivity type, and through which charge carriers from the source region drift to reach the drain region after passing through the channel. The composite drift region includes a first section adjacent the channel, a second section adjacent the drain region, and a third section disposed between the first and second sections. The first and second sections have a lower effective dopant concentration level than the third section.