公开(公告)号：US20070278595A1

公开(公告)日：2007-12-06

申请号：US11309376

申请日：2006-08-02

Applicant: Hsiao-Che Wu

Inventor： Hsiao-Che Wu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: A multi-fin field effect transistor includes a substrate, an oxide layer, a conductive layer, a gate oxide layer, and a doped region is provided. The substrate is surrounded by a trench, and there are at least two fin-type silicon layers formed in the substrate in a region prepared to form a gate thereon. The oxide layer is disposed in the trench and the top surface of the oxide layer is lower than that of the fin-type silicon layers. The conductive layer is disposed in the region prepared to form a gate. The top surface of the conductive layer is higher than that of the fin-type silicon layers. The gate oxide layer is disposed between the conductive layer and the fin-type silicon layers and disposed between the conductive layer and the substrate. The doped region is disposed in the substrate on both sides of the conductive layer.

Abstract translation: 提供了一种多鳍场效应晶体管，其包括衬底，氧化物层，导电层，栅极氧化物层和掺杂区域。 衬底被沟槽包围，并且在准备在其上形成栅极的区域中在衬底中形成有至少两个鳍型硅层。 氧化物层设置在沟槽中，氧化物层的上表面比翅片型硅层低。 导电层设置在准备形成栅极的区域中。 导电层的顶表面高于翅片型硅层的表面。 栅氧化层设置在导电层和翅片型硅层之间，并且设置在导电层和衬底之间。 掺杂区域设置在导电层两侧的衬底中。

公开(公告)号：US07510955B2

公开(公告)日：2009-03-31

申请号：US11309376

申请日：2006-08-02

Applicant: Hsiao-Che Wu

Inventor： Hsiao-Che Wu

IPC: H01L21/336

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: A multi-fin field effect transistor includes a substrate, an oxide layer, a conductive layer, a gate oxide layer, and a doped region is provided. The substrate is surrounded by a trench, and there are at least two fin-type silicon layers formed in the substrate in a region prepared to form a gate thereon. The oxide layer is disposed in the trench and the top surface of the oxide layer is lower than that of the fin-type silicon layers. The conductive layer is disposed in the region prepared to form a gate. The top surface of the conductive layer is higher than that of the fin-type silicon layers. The gate oxide layer is disposed between the conductive layer and the fin-type silicon layers and disposed between the conductive layer and the substrate. The doped region is disposed in the substrate on both sides of the conductive layer.

Abstract translation: 提供了一种多鳍场效应晶体管，其包括衬底，氧化物层，导电层，栅极氧化物层和掺杂区域。 衬底被沟槽包围，并且在准备在其上形成栅极的区域中在衬底中形成有至少两个鳍型硅层。 氧化物层设置在沟槽中，氧化物层的上表面比翅片型硅层低。 导电层设置在准备形成栅极的区域中。 导电层的顶表面高于翅片型硅层的表面。 栅氧化层设置在导电层和翅片型硅层之间，并且设置在导电层和衬底之间。 掺杂区域设置在导电层两侧的衬底中。

公开(公告)号：US20090039428A1

公开(公告)日：2009-02-12

申请号：US12053679

申请日：2008-03-24

Applicant: Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

Inventor： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

IPC: H01L29/00 ,  H01L21/20

CPC classification number: H01L21/76245

Abstract: A fabricating method for silicon on insulator is disclosed, and the fabricating method includes stripping the oxide and the nitride on the bottom surface of each of the trenches, forming a porous silicon on portions of the substrate by an anodizing process, spin coating a dielectric material to fill up the trenches and performing a thermal process to convert the porous silicon to an insulating layer.

Abstract translation: 公开了一种绝缘体硅的制造方法，其制造方法包括：剥离每个沟槽的底表面上的氧化物和氮化物，通过阳极氧化处理在衬底的部分上形成多孔硅，旋涂介电材料 填充沟槽并执行热处理以将多孔硅转化为绝缘层。

公开(公告)号：US07436526B2

公开(公告)日：2008-10-14

申请号：US11669165

申请日：2007-01-31

Applicant: Wen-Li Tsai ,  Yu-Min Tsai ,  Hsiao-Che Wu

Inventor： Wen-Li Tsai ,  Yu-Min Tsai ,  Hsiao-Che Wu

IPC: B29C65/00 ,  B29C65/02 ,  B32B37/00 ,  B32B38/00 ,  C23C16/52 ,  C23C14/54 ,  G01B11/14 ,  G01B11/28

CPC classification number: C23C14/544 ,  G01B11/0625 ,  G01B11/0675 ,  G01B11/0683 ,  H01L22/12 ,  H01L22/20

Abstract: A real-time system adapted to a PVD apparatus for monitoring and controlling film uniformity is described. The system includes a shielding plate, a monitoring device, and a data processing program. The shielding plate is disposed on an inner wall of a reaction chamber above a wafer stage. An opening in the center of the shielding plate exposes the wafer. The monitoring device including a scanner and a sensor respectively disposed on opposite sidewalls of the reaction chamber between the shielding plate and the wafer stage is used for measuring the flux of the particles on every portion of the wafer to acquire real-time uniformity data including a function of the wafer position and the flux. The data processing program compares the real-time uniformity data and reference uniformity data, and a feedback signal is outputted to the PVD apparatus to adjust the process parameter thereof for controlling film uniformity.

Abstract translation: 描述了适用于监测和控制膜均匀性的PVD设备的实时系统。 该系统包括屏蔽板，监视装置和数据处理程序。 屏蔽板设置在晶片台上方的反应室的内壁上。 屏蔽板中心的开口露出晶片。 包括扫描仪和分别设置在屏蔽板和晶片台之间的反应室的相对侧壁上的传感器的监视装置用于测量晶片每一部分上的颗粒的通量，以获得实时均匀性数据，包括 晶圆位置和通量的功能。 数据处理程序比较实时均匀性数据和参考均匀性数据，并且将反馈信号输出到PVD装置以调整其处理参数以控制膜均匀性。

公开(公告)号：US20080118631A1

公开(公告)日：2008-05-22

申请号：US11669165

申请日：2007-01-31

Applicant: Wen-Li Tsai ,  Yu-Min Tsai ,  Hsiao-Che Wu

Inventor： Wen-Li Tsai ,  Yu-Min Tsai ,  Hsiao-Che Wu

IPC: B05C11/00 ,  C23C14/54

CPC classification number: C23C14/544 ,  G01B11/0625 ,  G01B11/0675 ,  G01B11/0683 ,  H01L22/12 ,  H01L22/20

Abstract: A real-time system adapted to a PVD apparatus for monitoring and controlling film uniformity is described. The system includes a shielding plate, a monitoring device, and a data processing program. The shielding plate is disposed on an inner wall of a reaction chamber above a wafer stage. An opening in the center of the shielding plate exposes the wafer. The monitoring device including a scanner and a sensor respectively disposed on opposite sidewalls of the reaction chamber between the shielding plate and the wafer stage is used for measuring the flux of the particles on every portion of the wafer to acquire real-time uniformity data including a function of the wafer position and the flux. The data processing program compares the real-time uniformity data and reference uniformity data, and a feedback signal is outputted to the PVD apparatus to adjust the process parameter thereof for controlling film uniformity.

Abstract translation: 描述了适用于监测和控制膜均匀性的PVD设备的实时系统。 该系统包括屏蔽板，监视装置和数据处理程序。 屏蔽板设置在晶片台上方的反应室的内壁上。 屏蔽板中心的开口露出晶片。 包括扫描仪和分别设置在屏蔽板和晶片台之间的反应室的相对侧壁上的传感器的监视装置用于测量晶片每一部分上的颗粒的通量，以获得实时均匀性数据，包括 晶圆位置和通量的功能。 数据处理程序比较实时均匀性数据和参考均匀性数据，并且将反馈信号输出到PVD装置以调整其处理参数以控制膜均匀性。

公开(公告)号：US20060076595A1

公开(公告)日：2006-04-13

申请号：US11163600

申请日：2005-10-25

Applicant: Hsiao-Che Wu

Inventor： Hsiao-Che Wu

IPC: H01L29/94

CPC classification number: H01L27/10861 ,  H01L27/10867 ,  H01L27/10873 ,  H01L29/785

Abstract: A method of fabricating a dynamic random access memory cell is provided. A substrate having a patterned mask layer thereon and a deep trench therein is provided. The patterned mask layer exposes the deep trench. A deep trench capacitor is formed inside the deep trench. Thereafter, a trench is formed in the substrate on one side of the deep trench capacitor. The trench exposes a portion of the upper electrode of the deep trench capacitor and a portion of the substrate. After that, a semiconductor strip is formed in the trench. A gate dielectric layer is formed over the substrate to cover the exposed semiconductor strip and the substrate. A gate is formed over the gate dielectric layer such that the gate and the semiconductor strip crosses over each other, and the gate-covered portion of the semiconductor strip serves as a channel region.

Abstract translation: 提供一种制造动态随机存取存储单元的方法。 提供其上具有图案化掩模层并在其中具有深沟槽的衬底。 图案化掩模层暴露深沟槽。 在深沟槽内形成深沟槽电容器。 此后，在深沟槽电容器的一侧上的衬底中形成沟槽。 沟槽暴露了深沟槽电容器的上部电极的一部分和衬底的一部分。 之后，在沟槽中形成半导体条。 栅极电介质层形成在衬底上以覆盖暴露的半导体条和衬底。 栅极形成在栅极电介质层上，使得栅极和半导体条彼此交叉，并且半导体条的栅极覆盖部分用作沟道区。

公开(公告)号：US07005341B1

公开(公告)日：2006-02-28

申请号：US10711574

申请日：2004-09-25

Applicant: Hsiao-Che Wu

Inventor： Hsiao-Che Wu

IPC: H01L21/8234 ,  H01L21/8244

CPC classification number: H01L27/10867 ,  H01L27/10838 ,  H01L27/1087 ,  H01L27/10876 ,  H01L29/66181 ,  H01L29/945

Abstract: A method of fabricating a dynamic random access memory cell is provided. A substrate having a patterned mask layer thereon and a deep trench therein is provided. The patterned mask layer exposes the deep trench. A deep trench capacitor is formed inside the deep trench. Thereafter, a trench is formed in the substrate on one side of the deep trench capacitor. The trench exposes a portion of the upper electrode of the deep trench capacitor and a portion of the substrate. After that, a semiconductor strip is formed in the trench. A gate dielectric layer is formed over the substrate to cover the exposed semiconductor strip and the substrate. A gate is formed over the gate dielectric layer such that the gate and the semiconductor strip crosses over each other, and the gate-covered portion of the semiconductor strip serves as a channel region.

Abstract translation: 提供一种制造动态随机存取存储单元的方法。 提供其上具有图案化掩模层并在其中具有深沟槽的衬底。 图案化掩模层暴露深沟槽。 在深沟槽内形成深沟槽电容器。 此后，在深沟槽电容器的一侧上的衬底中形成沟槽。 沟槽暴露了深沟槽电容器的上部电极的一部分和衬底的一部分。 之后，在沟槽中形成半导体条。 栅极电介质层形成在衬底上以覆盖暴露的半导体条和衬底。 栅极形成在栅极电介质层上，使得栅极和半导体条彼此交叉，并且半导体条的栅极覆盖部分用作沟道区。

公开(公告)号：US06413384B1

公开(公告)日：2002-07-02

申请号：US09725219

申请日：2000-11-29

Applicant: Hsiao-Che Wu

Inventor： Hsiao-Che Wu

IPC: C23C1434

CPC classification number: C23C14/564

Abstract: The invention provides a method using plasma burn-in for maintaining cleanness within a vacuum chamber of a physical vapor deposition system, thereby reducing particles falling upon a processed wafer. When the operation pressure of the plasma for plasma burn-in is elevated above 10 mtorr, the distribution of the plasma is ever changed and able to enter the narrow space between the metal target side surface and an inner wall of the vacuum chamber so as to bombard the nodules on the side surface and to deposit a metal film upon the brittle metal compound film within the vacuum chamber for reducing the number of particles falling upon the wafer.

Abstract translation: 本发明提供一种使用等离子体老化来保持物理气相沉积系统的真空室内的清洁度的方法，从而减少落在加工晶片上的颗粒。 当等离子体老化的等离子体的操作压力升高到10mtorr以上时，等离子体的分布变化，能够进入金属靶侧面与真空室的内壁之间的狭窄空间，从而 轰击侧表面上的结节，并将金属膜沉积在真空室内的脆性金属化合物膜上，以减少落在晶片上的颗粒数。

公开(公告)号：US20090127618A1

公开(公告)日：2009-05-21

申请号：US12357410

申请日：2009-01-22

Applicant: Hsiao-Che Wu

Inventor： Hsiao-Che Wu

IPC: H01L29/78

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: A multi-fin field effect transistor includes a substrate, an oxide layer, a conductive layer, a gate oxide layer, and a doped region. The substrate is surrounded by a trench, and there are at least two fin-type silicon layers formed in the substrate in a region prepared to form a gate thereon. The oxide layer is disposed in the trench and the top surface of the oxide layer is lower than that of the fin-type silicon layers. The conductive layer is disposed in the region prepared to form a gate. The top surface of the conductive layer is higher than that of the fin-type silicon layers. The gate oxide layer is disposed between the conductive layer and the fin-type silicon layers and disposed between the conductive layer and the substrate. The doped region is disposed in the substrate on both sides of the conductive layer.

Abstract translation: 多鳍场效应晶体管包括衬底，氧化物层，导电层，栅极氧化物层和掺杂区域。 衬底被沟槽包围，并且在准备在其上形成栅极的区域中在衬底中形成有至少两个鳍型硅层。 氧化物层设置在沟槽中，氧化物层的上表面比翅片型硅层低。 导电层设置在准备形成栅极的区域中。 导电层的顶表面高于翅片型硅层的表面。 栅氧化层设置在导电层和翅片型硅层之间，并且设置在导电层和衬底之间。 掺杂区域设置在导电层两侧的衬底中。

公开(公告)号：US20080316674A1

公开(公告)日：2008-12-25

申请号：US12000145

申请日：2007-12-10

Applicant: Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

Inventor： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

IPC: H01G4/06 ,  H01G9/00

CPC classification number: H01L28/91 ,  H01G4/252 ,  H01G4/33 ,  H01L27/10852

Abstract: Capacitors and methods for fabricating the same are provided. An exemplary embodiment of a capacitor comprises a dielectric layer and a first conductive layer thereover. A supporting rib is embedded in the first conductive layer and extends along a first direction. A second conductive layer is embedded in the first conductive layer and extends along a second direction perpendicular with the first direction, wherein a portion of the second conductive layer forms across the supporting rib and is structurally supported by the supporting rib. A capacitor layer is formed between the first and second conductive layers to electrically insulate the first and second conductive layers.

Abstract translation: 提供了电容器及其制造方法。 电容器的示例性实施例包括电介质层和其上的第一导电层。 支撑肋嵌入在第一导电层中并且沿着第一方向延伸。 第二导电层被嵌入在第一导电层中并且沿着与第一方向垂直的第二方向延伸，其中第二导电层的一部分跨过支撑肋形成并且在结构上由支撑肋支撑。 在第一和第二导电层之间形成电容器层，以使第一和第二导电层电绝缘。