公开(公告)号：US20120133046A1

公开(公告)日：2012-05-31

申请号：US13037372

申请日：2011-03-01

申请人： Chun-Hsien Chien ,  John H. Lau ,  Hsiang-Hung Chang ,  Huan-Chun Fu ,  Tzu-Ying Kuo ,  Wen-Li Tsai

发明人： Chun-Hsien Chien ,  John H. Lau ,  Hsiang-Hung Chang ,  Huan-Chun Fu ,  Tzu-Ying Kuo ,  Wen-Li Tsai

IPC分类号： H01L23/48 ,  H01L21/28

CPC分类号： H01L23/481 ,  H01L21/6835 ,  H01L23/562 ,  H01L23/585 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05569 ,  H01L2224/0603 ,  H01L2224/06182 ,  H01L2224/11002 ,  H01L2224/13025 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2224/0231 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/05552

摘要： A semiconductor structure and a process thereof are provided. The semiconductor structure includes a semiconductor wafer having a first surface and a second surface opposite to the first surface, through silicon vias and a crack stopping slot. The through silicon vias are embedded in the semiconductor wafer and connected between the first surface and the second surface. The crack stopping slot is located in the periphery of the second surface of the semiconductor wafer. The depth of the crack stopping slot is less than or equal to the thickness of the semiconductor wafer. The process firstly provides a semiconductor wafer having through silicon vias. Then, the aforementioned crack stopping slot is formed at a back side of the semiconductor wafer opposite to the first surface. Next, the semiconductor wafer is thinned from the back side to expose a second end of each through silicon via.

摘要翻译： 提供半导体结构及其工艺。 半导体结构包括具有第一表面和与第一表面相对的第二表面的半导体晶片，通过硅通孔和裂纹停止槽。 贯通硅通孔嵌入在半导体晶片中并连接在第一表面和第二表面之间。 裂纹停止槽位于半导体晶片的第二表面的周边。 裂纹停止槽的深度小于或等于半导体晶片的厚度。 该方法首先提供具有硅通孔的半导体晶片。 然后，在半导体晶片的与第一表面相对的背面形成上述裂纹停止槽。 接下来，半导体晶片从背面变薄以暴露出每个通过硅通孔的第二端。

公开(公告)号：US20090039428A1

公开(公告)日：2009-02-12

申请号：US12053679

申请日：2008-03-24

申请人： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

发明人： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

IPC分类号： H01L29/00 ,  H01L21/20

CPC分类号： H01L21/76245

摘要： A fabricating method for silicon on insulator is disclosed, and the fabricating method includes stripping the oxide and the nitride on the bottom surface of each of the trenches, forming a porous silicon on portions of the substrate by an anodizing process, spin coating a dielectric material to fill up the trenches and performing a thermal process to convert the porous silicon to an insulating layer.

摘要翻译： 公开了一种绝缘体硅的制造方法，其制造方法包括：剥离每个沟槽的底表面上的氧化物和氮化物，通过阳极氧化处理在衬底的部分上形成多孔硅，旋涂介电材料 填充沟槽并执行热处理以将多孔硅转化为绝缘层。

公开(公告)号：US07436526B2

公开(公告)日：2008-10-14

申请号：US11669165

申请日：2007-01-31

申请人： Wen-Li Tsai ,  Yu-Min Tsai ,  Hsiao-Che Wu

发明人： Wen-Li Tsai ,  Yu-Min Tsai ,  Hsiao-Che Wu

IPC分类号： B29C65/00 ,  B29C65/02 ,  B32B37/00 ,  B32B38/00 ,  C23C16/52 ,  C23C14/54 ,  G01B11/14 ,  G01B11/28

CPC分类号： C23C14/544 ,  G01B11/0625 ,  G01B11/0675 ,  G01B11/0683 ,  H01L22/12 ,  H01L22/20

摘要： A real-time system adapted to a PVD apparatus for monitoring and controlling film uniformity is described. The system includes a shielding plate, a monitoring device, and a data processing program. The shielding plate is disposed on an inner wall of a reaction chamber above a wafer stage. An opening in the center of the shielding plate exposes the wafer. The monitoring device including a scanner and a sensor respectively disposed on opposite sidewalls of the reaction chamber between the shielding plate and the wafer stage is used for measuring the flux of the particles on every portion of the wafer to acquire real-time uniformity data including a function of the wafer position and the flux. The data processing program compares the real-time uniformity data and reference uniformity data, and a feedback signal is outputted to the PVD apparatus to adjust the process parameter thereof for controlling film uniformity.

摘要翻译： 描述了适用于监测和控制膜均匀性的PVD设备的实时系统。 该系统包括屏蔽板，监视装置和数据处理程序。 屏蔽板设置在晶片台上方的反应室的内壁上。 屏蔽板中心的开口露出晶片。 包括扫描仪和分别设置在屏蔽板和晶片台之间的反应室的相对侧壁上的传感器的监视装置用于测量晶片每一部分上的颗粒的通量，以获得实时均匀性数据，包括 晶圆位置和通量的功能。 数据处理程序比较实时均匀性数据和参考均匀性数据，并且将反馈信号输出到PVD装置以调整其处理参数以控制膜均匀性。

公开(公告)号：US20080118631A1

公开(公告)日：2008-05-22

申请号：US11669165

申请日：2007-01-31

申请人： Wen-Li Tsai ,  Yu-Min Tsai ,  Hsiao-Che Wu

发明人： Wen-Li Tsai ,  Yu-Min Tsai ,  Hsiao-Che Wu

IPC分类号： B05C11/00 ,  C23C14/54

CPC分类号： C23C14/544 ,  G01B11/0625 ,  G01B11/0675 ,  G01B11/0683 ,  H01L22/12 ,  H01L22/20

摘要： A real-time system adapted to a PVD apparatus for monitoring and controlling film uniformity is described. The system includes a shielding plate, a monitoring device, and a data processing program. The shielding plate is disposed on an inner wall of a reaction chamber above a wafer stage. An opening in the center of the shielding plate exposes the wafer. The monitoring device including a scanner and a sensor respectively disposed on opposite sidewalls of the reaction chamber between the shielding plate and the wafer stage is used for measuring the flux of the particles on every portion of the wafer to acquire real-time uniformity data including a function of the wafer position and the flux. The data processing program compares the real-time uniformity data and reference uniformity data, and a feedback signal is outputted to the PVD apparatus to adjust the process parameter thereof for controlling film uniformity.

摘要翻译： 描述了适用于监测和控制膜均匀性的PVD设备的实时系统。 该系统包括屏蔽板，监视装置和数据处理程序。 屏蔽板设置在晶片台上方的反应室的内壁上。 屏蔽板中心的开口露出晶片。 包括扫描仪和分别设置在屏蔽板和晶片台之间的反应室的相对侧壁上的传感器的监视装置用于测量晶片每一部分上的颗粒的通量，以获得实时均匀性数据，包括 晶圆位置和通量的功能。 数据处理程序比较实时均匀性数据和参考均匀性数据，并且将反馈信号输出到PVD装置以调整其处理参数以控制膜均匀性。

公开(公告)号：US07932565B2

公开(公告)日：2011-04-26

申请号：US12193502

申请日：2008-08-18

申请人： Hsiao Che Wu ,  Wen Li Tsai

发明人： Hsiao Che Wu ,  Wen Li Tsai

IPC分类号： H01L21/70

CPC分类号： H01L21/76232 ,  H01L21/7624 ,  H01L21/76264 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure comprises a semiconductor substrate, a device region positioned in the semiconductor substrate, an insulating region adjacent to the device region, an isolation structure positioned in the insulating region and including a bottle portion and a neck portion filled with a dielectric material, and a dielectric layer sandwiched between the device region and the insulation region.

摘要翻译： 集成电路结构包括半导体衬底，位于半导体衬底中的器件区域，与器件区域相邻的绝缘区域，位于绝缘区域中的隔离结构，其包括瓶部分和填充有电介质材料的颈部， 以及夹在器件区域和绝缘区域之间的电介质层。

公开(公告)号：US20100038745A1

公开(公告)日：2010-02-18

申请号：US12193502

申请日：2008-08-18

申请人： HSIAO CHE WU ,  WEN LI TSAI

发明人： HSIAO CHE WU ,  WEN LI TSAI

IPC分类号： H01L23/58

CPC分类号： H01L21/76232 ,  H01L21/7624 ,  H01L21/76264 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure comprises a semiconductor substrate, a device region positioned in the semiconductor substrate, an insulating region adjacent to the device region, an isolation structure positioned in the insulating region and including a bottle portion and a neck portion filled with a dielectric material, and a dielectric layer sandwiched between the device region and the insulation region.

摘要翻译： 集成电路结构包括半导体衬底，位于半导体衬底中的器件区域，与器件区域相邻的绝缘区域，位于绝缘区域中的隔离结构，其包括瓶部分和填充有电介质材料的颈部， 以及夹在器件区域和绝缘区域之间的电介质层。

公开(公告)号：US20090023268A1

公开(公告)日：2009-01-22

申请号：US12108306

申请日：2008-04-23

申请人： Hsiao-Che WU ,  Ming-Yen Li ,  Wen-Li Tsai

发明人： Hsiao-Che WU ,  Ming-Yen Li ,  Wen-Li Tsai

IPC分类号： H01L21/762

CPC分类号： H01L21/76205 ,  H01L21/823878

摘要： An isolation method of active area for semiconductor forms an isolated active area in a substrate. The substrate is a p-type silicon substrate. A pad oxide layer is formed on the substrate. A patterned sacrificial layer and an upper mask layer are formed on the pad oxide layer, where the upper mask layer is formed over the isolation region of the substrate. A gap is formed between the patterned sacrificial layer and the upper mask layer. An implantation process is performed to dope ions into the substrate through the gap, which forms an n-type barrier to surround the active areas. Lastly, the patterned sacrificial layer is stripped, and an anodization process is utilized to convert p-type bulk silicon into porous silicon. Then, an oxidation process is performed to oxidize the porous silicon to form a silicon dioxide isolation region for the active areas.

摘要翻译： 用于半导体的有源区的隔离方法在衬底中形成隔离的有源区。 衬底是p型硅衬底。 衬底氧化层形成在衬底上。 在衬垫氧化物层上形成图案化牺牲层和上掩模层，其中上掩模层形成在衬底的隔离区上。 在图案化的牺牲层和上掩模层之间形成间隙。 进行注入工艺以通过间隙将离子掺杂到衬底中，其形成围绕有源区的n型势垒。 最后，剥离图案化的牺牲层，并且使用阳极氧化工艺将p型体硅转化为多孔硅。 然后，进行氧化处理以氧化多孔硅以形成活性区的二氧化硅隔离区。

公开(公告)号：US20120205770A1

公开(公告)日：2012-08-16

申请号：US13186494

申请日：2011-07-20

申请人： Chiun-Yen TUNG ,  Kun-Hsien CHEN ,  Kai-Ying WANG ,  Wen-Li TSAI

发明人： Chiun-Yen TUNG ,  Kun-Hsien CHEN ,  Kai-Ying WANG ,  Wen-Li TSAI

IPC分类号： H01L29/872

CPC分类号： H01L29/872 ,  H01L29/8611

摘要： A Schottky diode with high antistatic capability has an N− type doped drift layer formed on an N+ type doped layer. The N− type doped drift layer has a surface formed with a protection ring. Inside the protection ring is a P-type doped area. The N− type doped drift layer surface is further formed with an oxide layer and a metal layer. The contact region between the metal layer and the N− type doped drift layer and the P-type doped area forms a Schottky contact. The P-type doped area has a low-concentration lower layer and a high-concentration upper layer, so that the surface ion concentration is high in the P-type doped area. The Schottky diode thus has such advantages of lowered forward voltage drop and high antistatic capability.

摘要翻译： 具有高抗静电能力的肖特基二极管具有形成在N +型掺杂层上的N型掺杂漂移层。 N型掺杂漂移层具有形成有保护环的表面。 保护环内部是P型掺杂区域。 N型掺杂漂移层表面还形成有氧化物层和金属层。 金属层和N型掺杂漂移层和P型掺杂区域之间的接触区域形成肖特基接触。 P型掺杂区域具有低浓度下层和高浓度上层，使得P型掺杂区域中的表面离子浓度高。 因此，肖特基二极管具有降低正向压降和高抗静电能力的优点。

公开(公告)号：US20100013004A1

公开(公告)日：2010-01-21

申请号：US12174110

申请日：2008-07-16

申请人： HSIAO CHE WU ,  MING YEN LI ,  WEN LI TSAI ,  BIN SIANG TSAI

发明人： HSIAO CHE WU ,  MING YEN LI ,  WEN LI TSAI ,  BIN SIANG TSAI

IPC分类号： H01L29/78

CPC分类号： H01L29/7834 ,  H01L21/28061 ,  H01L29/1037 ,  H01L29/6659 ,  H01L29/66621

摘要： A recessed channel transistor comprises a semiconductor substrate having a trench isolation structure, a gate structure having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate, two doped regions positioned at two sides of the upper block and above the lower block, and an insulation spacer positioned at a sidewall of the upper block and having a bottom end sandwiched between the upper block and the doped regions. In particular, the two doped regions serves as the source and drain regions, respectively, and the lower block of the gate structure serves as the recessed gate of the recessed channel transistor.

摘要翻译： 凹陷沟道晶体管包括具有沟槽隔离结构的半导体衬底，在半导体衬底中具有下部块的栅极结构和位于半导体衬底上的上部块，位于上部块的两侧和下部块上方的两个掺杂区域 以及位于上块的侧壁处并且具有夹在上块和掺杂区之间的底端的绝缘垫片。 特别地，两个掺杂区域分别用作源极和漏极区，并且栅极结构的下部块用作凹陷沟道晶体管的凹入栅极。

公开(公告)号：US20080316674A1

公开(公告)日：2008-12-25

申请号：US12000145

申请日：2007-12-10

申请人： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

发明人： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

IPC分类号： H01G4/06 ,  H01G9/00

CPC分类号： H01L28/91 ,  H01G4/252 ,  H01G4/33 ,  H01L27/10852

摘要： Capacitors and methods for fabricating the same are provided. An exemplary embodiment of a capacitor comprises a dielectric layer and a first conductive layer thereover. A supporting rib is embedded in the first conductive layer and extends along a first direction. A second conductive layer is embedded in the first conductive layer and extends along a second direction perpendicular with the first direction, wherein a portion of the second conductive layer forms across the supporting rib and is structurally supported by the supporting rib. A capacitor layer is formed between the first and second conductive layers to electrically insulate the first and second conductive layers.

摘要翻译： 提供了电容器及其制造方法。 电容器的示例性实施例包括电介质层和其上的第一导电层。 支撑肋嵌入在第一导电层中并且沿着第一方向延伸。 第二导电层被嵌入在第一导电层中并且沿着与第一方向垂直的第二方向延伸，其中第二导电层的一部分跨过支撑肋形成并且在结构上由支撑肋支撑。 在第一和第二导电层之间形成电容器层，以使第一和第二导电层电绝缘。