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公开(公告)号：US06858485B2
公开(公告)日：2005-02-22
申请号：US10249780
申请日：2003-05-07
IPC分类号： H01L21/331 , H01L29/08 , H01L29/732 , H01L21/8238
CPC分类号： H01L29/66287 , H01L29/0804 , H01L29/732
摘要： A double-polysilicon, self-aligned bipolar transistor has a collector region formed in a doped semiconductor substrate, an intrinsic counterdoped base formed on the surface of the substrate and a doped emitter formed in the surface of the intrinsic base. Form an etch stop dielectric layer over the intrinsic base layer above the collector. Form a base contact layer of a conductive material over the etch stop dielectric layer and the intrinsic base layer. Form a second dielectric layer over the base contact layer. Etch a wide window through the dielectric layer and the base contact layer stopping the etching of the window at the etch stop dielectric layer. Form an island or a peninsula narrowing the wide window leaving at least one narrowed window within the wide window. Form sidewall spacers in the either the wide window or the narrowed window. Fill the windows with doped polysilicon to form an extrinsic emitter. Form an emitter below the extrinsic emitter in the surface of the intrinsic base.
摘要翻译： 双重多晶硅自对准双极晶体管具有在掺杂半导体衬底中形成的集电极区域，形成在衬底表面上的本征反掺杂基底和形成在本征基底表面上的掺杂发射极。 在收集器上方的本征基底层上形成蚀刻停止介电层。 在蚀刻停止介电层和本征基极层上形成导电材料的基底接触层。 在基底接触层上形成第二介电层。 通过介电层和基底接触层蚀刻宽窗口，停止在蚀刻停止介电层处的窗口的蚀刻。 形成一个岛屿或一个半岛，缩小广阔的窗户，在宽阔的窗口内至少留出一个狭窄的窗户。 在宽窗口或狭窄的窗户中形成侧壁间隔物。 用掺杂多晶硅填充窗口以形成外部发射极。 在本征基表面的外部发射极之下形成发射体。
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公开(公告)号：US07180157B2
公开(公告)日：2007-02-20
申请号：US10978775
申请日：2004-11-01
IPC分类号： H01L27/082
CPC分类号： H01L29/66287 , H01L29/0804 , H01L29/732
摘要： A double-polysilicon, self-aligned bipolar transistor has a collector region formed in a doped semiconductor substrate, an intrinsic counterdoped base formed on the surface of the substrate and a doped intrinsic emitter formed in the surface of the intrinsic base. An etch stop insulator layer overlies the intrinsic base layer above the collector. A base contact layer of a conductive material overlies the etch stop dielectric layer and the intrinsic base layer. A dielectric layer overlies the base contact layer. A wide window extends through the insulator layer and the base contact layer down to the insulator layer. An island or a peninsula is formed in the wide window leaving at least one narrowed window within the wide window, with sidewall spacers in either the wide window or the narrowed window. The narrowed windows are filled with doped polysilicon forming an extrinsic emitter with the intrinsic emitter formed below the extrinsic emitter in the surface of the intrinsic base.
摘要翻译： 双重多晶硅，自对准双极晶体管具有在掺杂半导体衬底中形成的集电极区域，形成在衬底表面上的本征反掺杂基底和形成在本征基底表面的掺杂本征发射极。 蚀刻停止绝缘体层覆盖在收集器上方的本征基极层。 导电材料的基极接触层覆盖在蚀刻停止介电层和本征基极层之间。 电介质层覆盖在基底接触层上。 宽窗口延伸穿过绝缘体层和基底接触层向下延伸到绝缘体层。 在宽窗口中形成岛或半岛，在宽窗口内留下至少一个变窄的窗口，在宽窗口或狭窄窗口中具有侧壁间隔物。 变窄的窗口填充有掺杂的多晶硅，其形成外部发射极，本征发射极在本征基极表面的外部发射极之下形成。
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公开(公告)号：US07741186B2
公开(公告)日：2010-06-22
申请号：US11946940
申请日：2007-11-29
IPC分类号： H01L21/8222
CPC分类号： H01L29/66242 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/41708 , H01L29/42304 , H01L29/66272 , H01L29/732 , H01L29/7378
摘要： The mobility of charge carriers in a bipolar (BJT) device is increased by creating compressive strain in the device to increase mobility of electrons in the device, and creating tensile strain in the device to increase mobility of holes in the device. The compressive and tensile strain are created by applying a stress film adjacent an emitter structure of the device and atop a base film of the device. In this manner, the compressive and tensile strain are located in close proximity to an intrinsic portion of the device. A suitable material for the stress film is nitride. The emitter structure may be “T-shaped”, having a lateral portion atop an upright portion, a bottom of the upright portion forms a contact to the base film, and the lateral portion overhangs the base film.
摘要翻译： 双极（BJT）器件中的载流子的迁移率通过在器件中产生压缩应变以增加器件中电子的迁移率而增加，并且在器件中产生拉伸应变以增加器件中的孔的移动性。 通过在装置的发射极结构附近施加应力膜并且在器件的基底上方施加应力膜来产生压缩和拉伸应变。 以这种方式，压缩和拉伸应变位于设备本身部分附近。 适用于应力膜的材料是氮化物。 发射体结构可以是“T形”，其具有在直立部分顶部的侧面部分，直立部分的底部形成与基底膜的接触，并且侧向部分悬垂在基底膜上。
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14.发明授权Method of fabricating self-aligned bipolar transistor having tapered collector 有权制造具有锥形集电极的自对准双极晶体管的方法公开(公告)号：US07615457B2
公开(公告)日：2009-11-10
申请号：US12220521
申请日：2008-07-25
申请人： Hiroyuki Akatsu , Rama Divakaruni , Gregory G. Freeman , David R. Greenberg , Marwan H. Khater , William R. Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Gregory G. Freeman , David R. Greenberg , Marwan H. Khater , William R. Tonti
IPC分类号： H01L21/265 , H01L27/102
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/7378
摘要： A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The collector pedestal can be formed on a surface of a collector active region exposed within an opening extending through first and second overlying dielectric regions, where the opening defines vertically aligned edges of the first and second dielectric regions.
摘要翻译： 提供了一种用于制造双极晶体管的方法，该双极晶体管包括具有上部基本上平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁的锥形，即截头锥形收集器基座，上表面具有 比下表面小得多的面积。 收集器基座可以形成在暴露在通过第一和第二覆盖介质区域延伸的开口内的集电极有源区域的表面上，其中开口限定第一和第二电介质区域的垂直对齐的边缘。
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公开(公告)号：US20090073758A1
公开(公告)日：2009-03-19
申请号：US11857757
申请日：2007-09-19
申请人： Gregory G. Freeman , Qingqing Liang , Mario M. Pelella , Carl J. Radens , Huicai Zhong , Huilong Zhu
发明人： Gregory G. Freeman , Qingqing Liang , Mario M. Pelella , Carl J. Radens , Huicai Zhong , Huilong Zhu
CPC分类号： G11C11/412
摘要： The embodiments of the invention provide SRAM cells with asymmetric floating-body pass-gate transistors. More specifically, a semiconductor device includes an SRAM cell, a first pass-gate transistor, and a second pass-gate transistor. The first pass-gate transistor is connected to a first side of the SRAM cell, wherein the first pass-gate transistor comprises a first drain region and a first source region. The second pass-gate transistor is connected to a second side of the SRAM cell, wherein the second side is opposite the first side. The second pass-gate transistor comprises a second source region and a second drain region. Furthermore, the first source region and/or the second source region comprise a xenon implant. The first drain region and the second drain region each lack a xenon implant.
摘要翻译： 本发明的实施例提供具有非对称浮体通过栅极晶体管的SRAM单元。 更具体地，半导体器件包括SRAM单元，第一通过栅极晶体管和第二通过栅极晶体管。 第一栅极晶体管连接到SRAM单元的第一侧，其中第一栅极晶体管包括第一漏极区域和第一源极区域。 第二通栅晶体管连接到SRAM单元的第二侧，其中第二侧与第一侧相对。 第二通栅晶体管包括第二源区和第二漏区。 此外，第一源区和/或第二源区包括氙植入物。 第一漏区和第二漏区各自缺少氙植入物。
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16.发明申请Method of fabricating self-aligned bipolar transistor having tapered collector 有权制造具有锥形集电极的自对准双极晶体管的方法公开(公告)号：US20080318373A1
公开(公告)日：2008-12-25
申请号：US12220521
申请日：2008-07-25
申请人： Hiroyuki Akatsu , Rama Divakaruni , Gregory G. Freeman , David R. Greenberg , Marwan H. Khater , William R. Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Gregory G. Freeman , David R. Greenberg , Marwan H. Khater , William R. Tonti
IPC分类号： H01L21/8238
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/7378
摘要： A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The collector pedestal can be formed on a surface of a collector active region exposed within an opening extending through first and second overlying dielectric regions, where the opening defines vertically aligned edges of the first and second dielectric regions.
摘要翻译： 提供了一种用于制造双极晶体管的方法，该双极晶体管包括锥形的，即截头锥形的收集器基座，其具有上部基本平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁，上表面具有 比下表面小得多的面积。 收集器基座可以形成在暴露在通过第一和第二覆盖介质区域延伸的开口内的集电极有源区域的表面上，其中开口限定第一和第二电介质区域的垂直对齐的边缘。
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17.发明申请公开(公告)号：US20050233535A1
公开(公告)日：2005-10-20
申请号：US11150894
申请日：2005-06-13
IPC分类号： H01L29/737 , H01L21/331 , H01L21/8222 , H01L29/10 , H01L29/732 , H01L21/328 , H01L29/70
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/732
摘要： A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrinsic base to the emitter is accomplished by forming the extrinsic base in two regions. First, a first material of silicon or polysilicon having a first doping concentration is provided to form an outer extrinsic base region. Then a first opening is formed in the first material layer by lithography within which a dummy emitter pedestal is formed, which results in forming a trench between the sidewall of the first opening and the dummy pedestal. A second material of a second doping concentration is then provided inside the trench forming a distinct inner extrinsic base extension region to self-align the raised extrinsic base edge to the dummy pedestal edge. Since the emitter is formed where the dummy pedestal existed, the extrinsic base is also self-aligned to the emitter. The silicon or polysilicon forming the inner extrinsic base extension region can also be grown in the trench with selective or non-selective epitaxy.
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公开(公告)号：US20090079026A1
公开(公告)日：2009-03-26
申请号：US11860851
申请日：2007-09-25
IPC分类号： H01L29/00 , H01L21/762
CPC分类号： H01L29/0603 , H01L21/76224 , H01L29/1025 , H01L29/1054 , H01L29/84
摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.
摘要翻译： 在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。 通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。 应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。 氧化硅材料沉积在深沟槽中，平坦化和凹陷。 去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。 应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。
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公开(公告)号：US07329941B2
公开(公告)日：2008-02-12
申请号：US10710548
申请日：2004-07-20
IPC分类号： H01L27/082
CPC分类号： H01L29/66242 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/41708 , H01L29/42304 , H01L29/66272 , H01L29/732 , H01L29/7378
摘要： The mobility of charge carriers in a bipolar (BJT) device is increased by creating compressive strain in the device to increase mobility of electrons in the device, and creating tensile strain in the device to increase mobility of holes in the device. The compressive and tensile strain are created by applying a stress film adjacent an emitter structure of the device and atop a base film of the device. In this manner, the compressive and tensile strain are located in close proximity to an intrinsic portion of the device. A suitable material for the stress film is nitride. The emitter structure may be “T-shaped”, having a lateral portion atop an upright portion, a bottom of the upright portion forms a contact to the base film, and the lateral portion overhangs the base film.
摘要翻译： 双极（BJT）器件中的载流子的迁移率通过在器件中产生压缩应变以增加器件中电子的迁移率而增加，并且在器件中产生拉伸应变以增加器件中的孔的移动性。 通过在装置的发射极结构附近施加应力膜并且在器件的基底上方施加应力膜来产生压缩和拉伸应变。 以这种方式，压缩和拉伸应变位于设备本身部分附近。 适用于应力膜的材料是氮化物。 发射体结构可以是“T形”，其具有在直立部分顶部的侧面部分，直立部分的底部形成与基底膜的接触，并且侧向部分悬垂在基底膜上。
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公开(公告)号：US07217988B2
公开(公告)日：2007-05-15
申请号：US10709905
申请日：2004-06-04
申请人： David C. Ahlgren , Gregory G. Freeman , Francois Pagette , Christopher M. Schnabel , Anna W. Topol
发明人： David C. Ahlgren , Gregory G. Freeman , Francois Pagette , Christopher M. Schnabel , Anna W. Topol
IPC分类号： H01L27/082
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved fT, Fmax and drive current.
摘要翻译： 双极晶体管具有通过金属化直接接触基极 - 集电极结下方的集电极，以降低集电极电阻。 消除了常规的通孔和掩埋层以及它们的相关电阻。 晶体管非常隔离，几乎消除了良好的衬底电容和器件到器件的漏电流。 该结构提供了改进的电性能，包括改进的f T，F max和驱动电流。
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