公开(公告)号：US20180025973A1

公开(公告)日：2018-01-25

申请号：US15715654

申请日：2017-09-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： HuiLi Fu ,  Xiaodong Zhang ,  Jyh Rong Lin ,  Zhiqiang Ma

IPC: H01L23/528 ,  H01L23/49

Abstract: The present embodiments provides a chip, including a carrier, a redistribution structure, and multiple packaging function modules, where the multiple packaging function modules each have at least a part wrapped by a colloid, and are fastened to the redistribution structure side by side; the redistribution structure is fastened to the carrier, and the redistribution structure includes one or more redistribution metal layers; the redistribution metal layer communicatively connects the multiple packaging function modules and the carrier. The redistribution structure further includes one or more interconnect metal layers, and the interconnect metal layer is communicatively connected to at least two packaging function modules so as to provide a signal path between the at least two packaging function modules. In the chip, two packaging function modules are placed on the carrier side by side, and a signal path is established between the two packaging function modules by using the redistribution structure.

公开(公告)号：US11276645B2

公开(公告)日：2022-03-15

申请号：US16997003

申请日：2020-08-19

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Nan Zhao ,  Wenxu Xie ,  Junlei Tao ,  Shanghsuan Chiang ,  HuiLi Fu

IPC: H01L23/12 ,  H01L23/34 ,  H01L23/48 ,  H01L21/00 ,  H01L21/44 ,  H05K7/20 ,  H05K1/00 ,  H05K7/00 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00

Abstract: A chip and a packaging method thereof. In the chip, first solder pads in a first solder pad array on a first substrate are attached to corresponding second pins in second pin arrays on different dies to implement short-distance and high-density interconnection of the different dies. A molding body is used to wrap a first pin, a second pin, a first solder pad, and the first substrate, so that a fan-out unit and the first substrate are molded into an integral structure. In the integral structure, bottoms of first pins that are in a first pin array on a die and that are electrically connected to a periphery of the chip are not wrapped by the molding body.

公开(公告)号：US20200280132A1

公开(公告)日：2020-09-03

申请号：US16872920

申请日：2020-05-12

Applicant: Huawei Technologies Co., Ltd.

Inventor： Liangsheng Liu ,  Xinhong Li ,  HuiLi Fu

IPC: H01Q9/04 ,  H01Q1/22 ,  H01Q21/06 ,  H01Q23/00 ,  H01Q21/00 ,  H01Q1/48

Abstract: A patch antenna unit includes a first support layer, a substrate, a second support layer, and an integrated circuit that are stacked. One radiation patch is attached to the first support layer, and one radiation patch is attached to the second support layer. A ground layer is disposed on the second support layer, a coupling slot is disposed on the ground layer, and a feeder corresponding to the coupling slot is disposed on the second support layer. The integrated circuit is connected to the first ground layer and the feeder. In the foregoing specific technical solution, a four-layer substrate is used for fabrication.

公开(公告)号：US10607913B2

公开(公告)日：2020-03-31

申请号：US15797549

申请日：2017-10-30

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： HuiLi Fu ,  Shujie Cai ,  Feiyu Luo

IPC: H01L23/36 ,  H01L23/367 ,  H01L21/02 ,  H01L21/768 ,  H01L23/31 ,  H01L23/528 ,  H01L23/00

Abstract: The present invention provide an IC die, including an underlay; an active component; an interconnection layer, covering the active component, where the interconnection layer includes multiple metal layers and multiple dielectric layers, the multiple metal layers and the multiple dielectric layers are alternately arranged, a metal layer whose distance to the active component is the farthest in the multiple metal layers includes metal cabling and a metal welding pad; and a heat dissipation layer, where the heat dissipation layer covers a region above the interconnection layer except a position corresponding to the metal welding pad, the heat dissipation layer is located under a package layer, the package layer includes a plastic packaging material, and the heat dissipation layer includes an electrical-insulating material whose heat conductivity is greater than a preset value.

公开(公告)号：US10475741B2

公开(公告)日：2019-11-12

申请号：US15715654

申请日：2017-09-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： HuiLi Fu ,  Xiaodong Zhang ,  Jyh Rong Lin ,  Zhiqiang Ma

IPC: H01L23/528 ,  H01L21/56 ,  H01L23/49 ,  H01L23/532

Abstract: The present embodiments provides a chip, including a carrier, a redistribution structure, and multiple packaging function modules, where the multiple packaging function modules each have at least a part wrapped by a colloid, and are fastened to the redistribution structure side by side; the redistribution structure is fastened to the carrier, and the redistribution structure includes one or more redistribution metal layers; the redistribution metal layer communicatively connects the multiple packaging function modules and the carrier. The redistribution structure further includes one or more interconnect metal layers, and the interconnect metal layer is communicatively connected to at least two packaging function modules so as to provide a signal path between the at least two packaging function modules. In the chip, two packaging function modules are placed on the carrier side by side, and a signal path is established between the two packaging function modules by using the redistribution structure.

公开(公告)号：US20180308789A1

公开(公告)日：2018-10-25

申请号：US16023181

申请日：2018-06-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Nan Zhao ,  Wenxu Xie ,  Xiaodong Zhang ,  HuiLi Fu

IPC: H01L23/485 ,  H01L23/49 ,  H01L23/00 ,  H01L21/56 ,  H01L23/367

CPC classification number: H01L23/485 ,  H01L21/563 ,  H01L23/3672 ,  H01L23/49 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2924/15159 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/3025

Abstract: The invention discloses a packaging structure, including a substrate, a fan-out unit, and a wiring layer. The fan-out unit includes a first chip and a second chip. The first chip includes a first pin array, and the second chip includes a second pin array. The fan-out unit further includes a third pin array. The first pin array, the second pin array, and the third pin array are all disposed facing the substrate. The wiring layer bridges over between the first pin array and the second pin array, and is configured to connect each first pin in the first pin array to a corresponding second pin in the second pin array. The substrate is provided with a soldering pad that is electrically connected to a wiring layer in the substrate, and the third pin array is connected to the soldering pad.

公开(公告)号：US20180190566A1

公开(公告)日：2018-07-05

申请号：US15905044

申请日：2018-02-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： HuiLi Fu ,  Jyh Rong Lin ,  Shujie Cai

IPC: H01L23/373 ,  H01L23/367 ,  H01L21/48

CPC classification number: H01L23/3733 ,  H01L21/4871 ,  H01L21/4882 ,  H01L23/3672 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/42 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152

Abstract: An apparatus includes a circuit device, a heat sink fin, and a thermal interface material layer. The thermal interface material layer is thermally coupled to the circuit device and the heat sink fin. The thermal interface material layer includes a first alloy layer, a nanometal particle layer, and a second alloy layer. The first alloy layer is thermally coupled to the circuit device. The nanometal particle layer is thermally coupled to the first alloy layer. The nanometal particle layer includes nanometal particles and an intermediate mixture.