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    Reconfigurable logic device using spin accumulation and diffusion
    11.
    发明授权
    Reconfigurable logic device using spin accumulation and diffusion 有权
    可重构逻辑器件使用自旋积累和扩散

    公开(公告)号：US08421060B2

    公开(公告)日：2013-04-16

    申请号：US12684586

    申请日：2010-01-08

    申请人： Hyun Cheol Koo ,  Suk Hee Han ,  Joon Yeon Chang ,  Hyung Jun Kim ,  Jang Hae Ku

    发明人： Hyun Cheol Koo ,  Suk Hee Han ,  Joon Yeon Chang ,  Hyung Jun Kim ,  Jang Hae Ku

    IPC分类号： H01L29/82 ,  H01L29/66

    CPC分类号： H01L29/66984 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L29/0665 ,  H01L29/1606 ,  H01L29/7783

    摘要： A logic device includes: a substrate having a channel layer; two input terminal patterns of ferromagnetic material formed on the substrate and spaced apart from each other along a longitudinal direction of the channel layer so as to serve as the input terminals of a logic gate; and an output terminal pattern of ferromagnetic material formed on the substrate and disposed between the two input terminal patterns to serve as an output terminal of the logic gate. The output terminal pattern reads an output voltage by using spin accumulation and diffusion of electron spins which are injected into the channel layer from the input terminal patterns.

    摘要翻译： 逻辑器件包括：具有沟道层的衬底; 铁磁材料的两个输入端子图案形成在基板上并且沿着沟道层的纵向方向彼此间隔开，以便用作逻辑门的输入端; 以及形成在所述基板上并且设置在所述两个输入端子图案之间以用作所述逻辑门的输出端子的铁磁材料的输出端子图案。 输出端子图案通过使用从输入端子图案注入到沟道层中的电子自旋的自旋累积和扩散来读取输出电压。

    SPIN TRANSISTOR USING N-TYPE AND P-TYPE DOUBLE CARRIER SUPPLY LAYER STRUCTURE
    12.
    发明申请
    SPIN TRANSISTOR USING N-TYPE AND P-TYPE DOUBLE CARRIER SUPPLY LAYER STRUCTURE 有权
    使用N型和P型双载波供电层结构的旋转晶体管

    公开(公告)号：US20110284937A1

    公开(公告)日：2011-11-24

    申请号：US12858702

    申请日：2010-08-18

    申请人： Hyung Jun KIM ,  Jin Dong Song ,  Hyun Cheol Koo ,  Kyung Ho Kim ,  Suk Hee Han

    发明人： Hyung Jun KIM ,  Jin Dong Song ,  Hyun Cheol Koo ,  Kyung Ho Kim ,  Suk Hee Han

    IPC分类号： H01L29/82

    CPC分类号： H01L29/66984 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/18 ,  Y10S257/902

    摘要： A spin transistor that includes: a semiconductor substrate including an upper cladding layer and a lower cladding layer, and a channel layer interposed between the upper and lower cladding layers; a ferromagnetic source and a ferromagnetic drain formed on the semiconductor substrate and spaced from each other in a length direction of the channel layer; and a gate electrode formed on the semiconductor substrate between the source and the drain and having applied a gate voltage thereto to control a spin precession of an electron passing through the channel layer, wherein the semiconductor substrate includes a first carrier supply layer of a first conductivity type disposed below the lower cladding layer and supplying carriers to the channel layer, and a second carrier supply layer of a second conductivity type opposite to the first conductivity type formed on the upper cladding layer and supplying the carriers to the channel layer.

    摘要翻译： 一种自旋晶体管，包括：包括上包层和下包层的半导体衬底，以及介于上包层和下包层之间的沟道层; 形成在所述半导体基板上并且在所述沟道层的长度方向上彼此间隔开的铁磁源和铁磁性漏极; 以及形成在所述源极和漏极之间的所述半导体衬底上并且施加了栅极电压以用于控制通过所述沟道层的电子的自旋进动的栅电极，其中所述半导体衬底包括具有第一导电性的第一载流子供应层 类型，其设置在所述下包层下方并且将沟道层供给到所述沟道层;以及第二导电类型的第二载流子供应层，其形成在所述上包层上并且将所述载流子提供给所述沟道层。

    Spin transistor using N-type and P-type double carrier supply layer structure
    13.
    发明授权
    Spin transistor using N-type and P-type double carrier supply layer structure 有权
    旋转晶体管采用N型和P型双载体供电层结构

    公开(公告)号：US08183611B2

    公开(公告)日：2012-05-22

    申请号：US12858702

    申请日：2010-08-18

    申请人： Hyung Jun Kim ,  Jin Dong Song ,  Hyun Cheol Koo ,  Kyung Ho Kim ,  Suk Hee Han

    发明人： Hyung Jun Kim ,  Jin Dong Song ,  Hyun Cheol Koo ,  Kyung Ho Kim ,  Suk Hee Han

    IPC分类号： H01L29/76

    CPC分类号： H01L29/66984 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/18 ,  Y10S257/902

    摘要： A spin transistor that includes: a semiconductor substrate including an upper cladding layer and a lower cladding layer, and a channel layer interposed between the upper and lower cladding layers; a ferromagnetic source and a ferromagnetic drain formed on the semiconductor substrate and spaced from each other in a length direction of the channel layer; and a gate electrode formed on the semiconductor substrate between the source and the drain and having applied a gate voltage thereto to control a spin precession of an electron passing through the channel layer, wherein the semiconductor substrate includes a first carrier supply layer of a first conductivity type disposed below the lower cladding layer and supplying carriers to the channel layer, and a second carrier supply layer of a second conductivity type opposite to the first conductivity type formed on the upper cladding layer and supplying the carriers to the channel layer.

    摘要翻译： 一种自旋晶体管，包括：包括上包层和下包层的半导体衬底，以及介于上包层和下包层之间的沟道层; 形成在所述半导体基板上并且在所述沟道层的长度方向上彼此间隔开的铁磁源和铁磁性漏极; 以及形成在所述源极和漏极之间的所述半导体衬底上并且施加了栅极电压以用于控制通过所述沟道层的电子的自旋进动的栅电极，其中所述半导体衬底包括具有第一导电性的第一载流子供应层 类型，其设置在所述下包层下方并且将沟道层供给到所述沟道层;以及第二导电类型的第二载流子供应层，其形成在所述上包层上并且将所述载流子提供给所述沟道层。

    P-type semiconductor device comprising type-2 quantum well and fabrication method thereof
    15.
    发明授权
    P-type semiconductor device comprising type-2 quantum well and fabrication method thereof 有权
    包括2型量子阱的P型半导体器件及其制造方法

    公开(公告)号：US08586964B2

    公开(公告)日：2013-11-19

    申请号：US12911560

    申请日：2010-10-25

    申请人： Jin-Dong Song ,  Sang Hoon Shin ,  Hyung-jun Kim ,  Hyun Cheol Koo ,  Suk Hee Han ,  Joonyeon Chang

    发明人： Jin-Dong Song ,  Sang Hoon Shin ,  Hyung-jun Kim ,  Hyun Cheol Koo ,  Suk Hee Han ,  Joonyeon Chang

    IPC分类号： H01L29/15

    CPC分类号： H01L29/7783 ,  B82Y10/00 ,  H01L29/122

    摘要： Disclosed herein are a method of generating a two-dimensional hole gas (2DHG) using a type-2 quantum well formed using semiconductors with different electron affinities or band gap, and a high-speed p-type semiconductor device using the 2DHG. To this end, the method includes providing a semiconductor substrate; growing a first semiconductor layer on the semiconductor substrate, growing a second semiconductor layer with a different electron affinity or band gap from the first semiconductor layer on the first semiconductor layer, and growing a third semiconductor layer with a different electron affinity or band gap from the second semiconductor layer, thereby forming a type-2 quantum well; and forming a p-type doping layer in the vicinity of the type-2 quantum well, thereby generating the 2DHG.

    摘要翻译： 本文公开了使用具有不同电子亲和性或带隙的半导体形成的2型量子阱和使用该2DHG的高速p型半导体器件来生成二维空穴气体（2DHG）的方法。 为此，该方法包括提供半导体衬底; 在所述半导体衬底上生长第一半导体层，在所述第一半导体层上生长具有与所述第一半导体层不同的电子亲和性或带隙的第二半导体层，以及生长具有与所述第一半导体层不同的电子亲和性或带隙的第三半导体层 第二半导体层，从而形成2型量子阱; 并在2型量子阱附近形成p型掺杂层，从而生成2DHG。

    P-TYPE SEMICONDUCTOR DEVICE COMPRISING TYPE-2 QUANTUM WELL AND FABRICATION METHOD THEREOF
    16.
    发明申请
    P-TYPE SEMICONDUCTOR DEVICE COMPRISING TYPE-2 QUANTUM WELL AND FABRICATION METHOD THEREOF 有权
    包含2型量子阱的P型半导体器件及其制造方法

    公开(公告)号：US20120007045A1

    公开(公告)日：2012-01-12

    申请号：US12911560

    申请日：2010-10-25

    申请人： JIN-DONG SONG ,  Sang Hoon Shin ,  Hyung-jun Kim ,  Hyun Cheol Koo ,  Suk Hee Han ,  Joonyeon Chang

    发明人： JIN-DONG SONG ,  Sang Hoon Shin ,  Hyung-jun Kim ,  Hyun Cheol Koo ,  Suk Hee Han ,  Joonyeon Chang

    IPC分类号： H01L29/15 ,  H01L21/20

    CPC分类号： H01L29/7783 ,  B82Y10/00 ,  H01L29/122

    摘要： Disclosed herein are a method of generating a two-dimensional hole gas (2DHG) using a type-2 quantum well formed using semiconductors with different electron affinities or band gap, and a high-speed p-type semiconductor device using the 2DHG. To this end, the method includes providing a semiconductor substrate; growing a first semiconductor layer on the semiconductor substrate, growing a second semiconductor layer with a different electron affinity or band gap from the first semiconductor layer on the first semiconductor layer, and growing a third semiconductor layer with a different electron affinity or band gap from the second semiconductor layer, thereby forming a type-2 quantum well; and forming a p-type doping layer in the vicinity of the type-2 quantum well, thereby generating the 2DHG.

    摘要翻译： 本文公开了使用具有不同电子亲和性或带隙的半导体形成的2型量子阱和使用该2DHG的高速p型半导体器件来生成二维空穴气体（2DHG）的方法。 为此，该方法包括提供半导体衬底; 在所述半导体衬底上生长第一半导体层，在所述第一半导体层上生长具有与所述第一半导体层不同的电子亲和性或带隙的第二半导体层，以及生长具有与所述第一半导体层不同的电子亲和性或带隙的第三半导体层 第二半导体层，从而形成2型量子阱; 并在2型量子阱附近形成p型掺杂层，从而生成2DHG。