公开(公告)号：US20240204082A1

公开(公告)日：2024-06-20

申请号：US18543933

申请日：2023-12-18

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Boon Teik Chan ,  Shairfe Muhammad Salahuddin ,  Julien Ryckaert ,  Bilal Chehab ,  Hsiao-Hsuan Liu

IPC: H01L29/66 ,  H01L21/306

CPC classification number: H01L29/66545 ,  H01L21/306 ,  H01L29/66439

Abstract: Example embodiments relate to methods for forming a semiconductor device. One example method includes forming a device structure on a substrate, where the device structure includes a device layer stack that includes a bottom device sub-stack that includes at least one bottom channel layer and a top device sub-stack that includes at least one top channel layer, a sacrificial gate structure extending across the device layer stack, and bottom source/drain structures on opposite ends of at least one bottom channel layer. The method also includes forming an opening exposing the top device sub-stack, wherein forming the opening includes etching the sacrificial gate structure, forming a cut through the top device sub-stack by etching back the top device sub-stack from the opening and, subsequent to forming the cut, forming a functional gate stack on the at least one bottom channel layer.

公开(公告)号：US11374058B2

公开(公告)日：2022-06-28

申请号：US16559501

申请日：2019-09-03

Applicant: IMEC vzw

Inventor： Shairfe Muhammad Salahuddin ,  Alessio Spessot

IPC: H01L27/24 ,  H01L45/00 ,  H01L43/10 ,  H01L29/872

Abstract: The disclosed technology generally relates to a memory selector and to a memory device including the memory selector, and more particularly to the memory selector and the memory device implemented in a crossbar memory architecture. In one aspect, a memory selector for a crossbar memory architecture comprises a metal bottom electrode, a metal top electrode and an intermediate layer stack between and in contact with the metal top and bottom electrodes. A bottom Schottky barrier having a bottom Schottky barrier height (ΦB) is formed at the interface between the metal bottom electrode and the intermediate layer stack. A top Schottky barrier having a top Schottky barrier height (ΦT) is formed at the interface between the metal top electrode and the intermediate layer stack. The disclosed technology further relates to a random access memory (RAM) and a memory cell including the memory selector.

公开(公告)号：US11211404B2

公开(公告)日：2021-12-28

申请号：US16565112

申请日：2019-09-09

Applicant: IMEC vzw

Inventor： Shairfe Muhammad Salahuddin ,  Jan Van Houdt ,  Julien Ryckaert ,  Alessio Spessot

IPC: G11C11/22 ,  H01L27/1159 ,  G11C11/4096 ,  H01L27/108 ,  H01L27/11587 ,  H01L27/11592

Abstract: The disclosed technology is generally directed to semiconductor integrated circuit devices and more particularly to a three-transistor random access memory (3T RAM) device, and a method of fabricating and operating the same. In one aspect, a 3T RAM cell includes a ferroelectric-based field effect transistor (FeFET) having a first gate connected as a storage node and a second transistor connected between the FeFET and a read bit line having a second gate connected to a read word line. The 3T RAM cell also includes a third transistor connected between the storage node and a write bit line having a third gate connected to a write word line.

公开(公告)号：US20200075676A1

公开(公告)日：2020-03-05

申请号：US16559501

申请日：2019-09-03

Applicant: IMEC vzw

Inventor： Shairfe Muhammad Salahuddin ,  Alessio Spessot

IPC: H01L27/24 ,  H01L29/872 ,  H01L45/00 ,  H01L43/10

Abstract: The disclosed technology generally relates to a memory selector and to a memory device including the memory selector, and more particularly to the memory selector and the memory device implemented in a crossbar memory architecture. In one aspect, a memory selector for a crossbar memory architecture comprises a metal bottom electrode, a metal top electrode and an intermediate layer stack between and in contact with the metal top and bottom electrodes. A bottom Schottky barrier having a bottom Schottky barrier height (ΦB) is formed at the interface between the metal bottom electrode and the intermediate layer stack. A top Schottky barrier having a top Schottky barrier height (ΦT) is formed at the interface between the metal top electrode and the intermediate layer stack. The disclosed technology further relates to a random access memory (RAM) and a memory cell including the memory selector.

公开(公告)号：US20250087643A1

公开(公告)日：2025-03-13

申请号：US18816473

申请日：2024-08-27

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Shairfe Muhammad Salahuddin

IPC: H01L25/07 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

Abstract: A system includes at least two photovoltaic modules each comprising a respective module area being substantially perpendicular to the thickness of the corresponding photovoltaic module. Each of the at least two module areas comprises at least one of two first sides being substantially perpendicular to the thickness of the corresponding photovoltaic module and/or two second sides being substantially perpendicular to the thickness of the corresponding photovoltaic module. In this context, the at least two module areas are arranged in a substantially parallel manner with respect to each other and are shifted with respect to each other in an extension direction of the system. In addition to this, the at least two module areas are arranged in a staggering or alternating or ascending or descending manner with respect to an extension plane in the extension direction of the system.

公开(公告)号：US20240373617A1

公开(公告)日：2024-11-07

申请号：US18654367

申请日：2024-05-03

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Hsiao-Hsuan Liu ,  Boon Teik Chan ,  Shairfe Muhammad Salahuddin

IPC: H10B10/00

Abstract: A three-dimensional (3D) static random access memory (SRAM) cell includes two PU transistors arranged in a first tier, two PD transistors arranged in a second tier positioned above or below the first tier, and two PG transistors arranged in the first or second tier. The transistors can be fin transistors, and each PU and PD transistor can have a first and second number of fins, respectively. The transistors can also be nanosheet-based transistors, and each PU and PD transistor can have a first and a second nanosheet width, respectively.

公开(公告)号：US20240204081A1

公开(公告)日：2024-06-20

申请号：US18539021

申请日：2023-12-13

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Boon Teik Chan ,  Hsiao-Hsuan Liu ,  Shairfe Muhammad Salahuddin

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A method for forming a semiconductor device is disclosed. The method includes: forming a first bottom and top channel structures, and second bottom and top channel structures, and a sacrificial gate extending across the channel structures; forming an opening in the sacrificial gate, over the first top channel structure and forming a cut through the first top channel structure; forming a dielectric plug in the cut and the opening; removing the sacrificial gate and subsequently forming an RMG structure comprising a first gate stack on the first bottom channel structure and a second gate stack on the second bottom and top channel structures; forming pairs of S/D structures on the first bottom channel structure, the second bottom channel structure, and the second top channel structure; forming S/D contacts on the S/D structures; forming a trench for a cross-couple contact; and forming the cross-couple contact in the trench.

公开(公告)号：US20200152503A1

公开(公告)日：2020-05-14

申请号：US16577332

申请日：2019-09-20

Applicant: IMEC VZW

Inventor： Shairfe Muhammad Salahuddin ,  Alessio Spessot

IPC: H01L21/764 ,  H01L21/02 ,  H01L21/311 ,  H01L29/51

Abstract: A method for forming airgaps within an integrated electronic circuit implements a conformal layer and a nanosheet both of boron nitride. The method has advantages for the circuit due to special properties of boron nitride material. In particular, mechanical strength and heat dissipation are increased whereas electro-migration is limited. The method may be applied to the first interconnect layer of the integrated circuit, for reducing additionally capacitive interactions existing between gate electrode structures and source or drain contact structures.