公开(公告)号：US20200083234A1

公开(公告)日：2020-03-12

申请号：US16565112

申请日：2019-09-09

Applicant: IMEC vzw

Inventor： Shairfe Muhammad Salahuddin ,  Jan Van Houdt ,  Julien Ryckaert ,  Alessio Spessot

IPC: H01L27/1159 ,  H01L27/108 ,  G11C11/4096 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/11592

Abstract: The disclosed technology is generally directed to semiconductor integrated circuit devices and more particularly to a three-transistor random access memory (3T RAM) device, and a method of fabricating and operating the same. In one aspect, a 3T RAM cell includes a ferroelectric-based field effect transistor (FeFET) having a first gate connected as a storage node and a second transistor connected between the FeFET and a read bit line having a second gate connected to a read word line. The 3T RAM cell also includes a third transistor connected between the storage node and a write bit line having a third gate connected to a write word line.

公开(公告)号：US12164849B2

公开(公告)日：2024-12-10

申请号：US17039571

申请日：2020-09-30

Applicant: IMEC vzw

Inventor： Subrat Mishra ,  Pieter Weckx ,  Francky Catthoor ,  Alessio Spessot

IPC: G06F30/3308 ,  G06F30/367 ,  G06F30/392 ,  G06F30/398 ,  G06F115/06 ,  G06F119/04

Abstract: A system and method of simulating device aging based on a digital waveform representative of a workload of an electronic device are disclosed. In one aspect, the method comprises grouping contiguous sets of cycles into segments, each set corresponding to a segment. Each segment has values for a combination of segment parameters that are unique from each of the other segments and a start point that is separated from a start point of an adjacent segment by a pre-defined distance criterion. Grouping the sets into the segments comprises, for each segment: sampling one or more sequential cycles of the workload, generating the segment based on the sampled contiguous cycles having a period exceeding a threshold period, and determining the values for the combination of segment parameters. The method further comprises applying an aging model to the segments to simulate the aging. The segments are a representation of the digital waveform.

公开(公告)号：US11276606B2

公开(公告)日：2022-03-15

申请号：US16577332

申请日：2019-09-20

Applicant: IMEC VZW

Inventor： Shairfe Muhammad Salahuddin ,  Alessio Spessot

IPC: H01L21/764 ,  H01L21/02 ,  H01L21/311 ,  H01L29/51

Abstract: A method for forming airgaps within an integrated electronic circuit implements a conformal layer and a nanosheet both of boron nitride. The method has advantages for the circuit due to special properties of boron nitride material. In particular, mechanical strength and heat dissipation are increased whereas electro-migration is limited. The method may be applied to the first interconnect layer of the integrated circuit, for reducing additionally capacitive interactions existing between gate electrode structures and source or drain contact structures.

公开(公告)号：US20200211839A1

公开(公告)日：2020-07-02

申请号：US16719725

申请日：2019-12-18

Applicant: IMEC vzw

Inventor： Shairfe Muhammad Salahuddin ,  Alessio Spessot

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L29/10

Abstract: The disclosed technology generally relates to semiconductor devices and methods of manufacturing semiconductor devices such as both logic and memory semiconductor devices. In one aspect, a semiconductor device includes a semiconductor substrate having a channel region between a source and a drain region, a gate structure arranged to control the channel region and a dielectric structure arranged between the channel region and the gate structure. The dielectric structure includes a high-k dielectric layer or a high-k ferroelectric layer and at least one two dimensional (2D) hexagonal boron-nitride (h-BN) layer in direct contact with the high-k dielectric layer or the high-k ferroelectric layer.

公开(公告)号：US20220100939A1

公开(公告)日：2022-03-31

申请号：US17039571

申请日：2020-09-30

Applicant: IMEC vzw

Inventor： Subrat Mishra ,  Pieter Weckx ,  Francky Catthoor ,  Alessio Spessot

IPC: G06F30/3308 ,  G06F30/392

Abstract: A system and method of simulating device aging based on a digital waveform representative of a workload of an electronic device are disclosed. In one aspect, the method comprises grouping contiguous sets of cycles into segments, each set corresponding to a segment. Each segment has values for a combination of segment parameters that are unique from each of the other segments and a start point that is separated from a start point of an adjacent segment by a pre-defined distance criterion. Grouping the sets into the segments comprises, for each segment: sampling one or more sequential cycles of the workload, generating the segment based on the sampled contiguous cycles having a period exceeding a threshold period, and determining the values for the combination of segment parameters. The method further comprises applying an aging model to the segments to simulate the aging. The segments are a representation of the digital waveform.

公开(公告)号：US20210202480A1

公开(公告)日：2021-07-01

申请号：US17127424

申请日：2020-12-18

Applicant: IMEC vzw

Inventor： Eugenio Dentoni Litta ,  Alessio Spessot

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/112

Abstract: The disclosed technology relates generally to semiconductor devices and manufacturing methods thereof, and more particularly to field-effect transistors operating at different voltages and methods for integrating the same. In one aspect, a method of fabricating a semiconductor device comprises: a) providing a substrate and a first hardmask; b) next, providing a second hardmask over a first region of the first hardmask; c) next, forming a first set of hardmask fins in a second region of the first hardmask; d) next, masking the second region; e) next, providing a set of photoresist fins on the second hardmask; f) next, patterning the second hardmask and the first region by using the photoresist fins as a mask; g) next, forming a first set of semiconductor fins of a first height by etching the substrate; h) next, removing the mask provided in step d; i) next, forming a second set of semiconductor fins of a second height in the second region and extending the height of the first set of semiconductor fins to a third height in the first region, by etching the substrate by using the first and second sets of hardmask fins as masks.

公开(公告)号：US20200152503A1

公开(公告)日：2020-05-14

申请号：US16577332

申请日：2019-09-20

Applicant: IMEC VZW

Inventor： Shairfe Muhammad Salahuddin ,  Alessio Spessot

IPC: H01L21/764 ,  H01L21/02 ,  H01L21/311 ,  H01L29/51

Abstract: A method for forming airgaps within an integrated electronic circuit implements a conformal layer and a nanosheet both of boron nitride. The method has advantages for the circuit due to special properties of boron nitride material. In particular, mechanical strength and heat dissipation are increased whereas electro-migration is limited. The method may be applied to the first interconnect layer of the integrated circuit, for reducing additionally capacitive interactions existing between gate electrode structures and source or drain contact structures.

公开(公告)号：US20150171857A1

公开(公告)日：2015-06-18

申请号：US14570592

申请日：2014-12-15

Applicant: IMEC VZW

Inventor： Alessio Spessot ,  Moon Ju Cho

IPC: H03K17/16 ,  H03K17/687

CPC classification number: H03K17/165 ,  G01R31/2621 ,  H03K3/011 ,  H03K17/145 ,  H03K17/687

Abstract: A method for at least partially compensating for a change in threshold voltage level of a FET transistor induced by OFF-state stress degradation includes determining a signal indicative of a change in threshold voltage level of the FET with respect to a reference threshold voltage level, and applying a restoration signal to the FET. This restoration signal is adapted for shifting the threshold voltage level of the FET in a direction having opposite sign with respect to the change in threshold voltage level. Applying the restoration signal further includes taking into account the signal indicative of the change in threshold voltage level.

Abstract translation: 用于至少部分地补偿由关态状态应力劣化引起的FET晶体管的阈值电压电平的变化的方法包括：确定指示FET相对于参考阈值电压电平的阈值电压电平变化的信号;以及 向FET施加恢复信号。 该恢复信号适于相对于阈值电压电平的变化沿着具有相反符号的方向移动FET的阈值电压电平。 应用恢复信号还包括考虑指示阈值电压电平变化的信号。

公开(公告)号：US11374058B2

公开(公告)日：2022-06-28

申请号：US16559501

申请日：2019-09-03

Applicant: IMEC vzw

Inventor： Shairfe Muhammad Salahuddin ,  Alessio Spessot

IPC: H01L27/24 ,  H01L45/00 ,  H01L43/10 ,  H01L29/872

Abstract: The disclosed technology generally relates to a memory selector and to a memory device including the memory selector, and more particularly to the memory selector and the memory device implemented in a crossbar memory architecture. In one aspect, a memory selector for a crossbar memory architecture comprises a metal bottom electrode, a metal top electrode and an intermediate layer stack between and in contact with the metal top and bottom electrodes. A bottom Schottky barrier having a bottom Schottky barrier height (ΦB) is formed at the interface between the metal bottom electrode and the intermediate layer stack. A top Schottky barrier having a top Schottky barrier height (ΦT) is formed at the interface between the metal top electrode and the intermediate layer stack. The disclosed technology further relates to a random access memory (RAM) and a memory cell including the memory selector.

公开(公告)号：US11211404B2

公开(公告)日：2021-12-28

申请号：US16565112

申请日：2019-09-09

Applicant: IMEC vzw

Inventor： Shairfe Muhammad Salahuddin ,  Jan Van Houdt ,  Julien Ryckaert ,  Alessio Spessot

IPC: G11C11/22 ,  H01L27/1159 ,  G11C11/4096 ,  H01L27/108 ,  H01L27/11587 ,  H01L27/11592

Abstract: The disclosed technology is generally directed to semiconductor integrated circuit devices and more particularly to a three-transistor random access memory (3T RAM) device, and a method of fabricating and operating the same. In one aspect, a 3T RAM cell includes a ferroelectric-based field effect transistor (FeFET) having a first gate connected as a storage node and a second transistor connected between the FeFET and a read bit line having a second gate connected to a read word line. The 3T RAM cell also includes a third transistor connected between the storage node and a write bit line having a third gate connected to a write word line.