公开(公告)号：US09142776B2

公开(公告)日：2015-09-22

申请号：US13723009

申请日：2012-12-20

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Heng-Yuan Lee ,  Pang-Shiu Chen ,  Tai-Yuan Wu ,  Ching-Chiun Wang

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L45/1641 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1658

Abstract: A resistive random access memory and a method for fabricating the same are provided. The method includes forming a bottom electrode on a substrate; forming a metal oxide layer on the bottom electrode; forming an oxygen atom gettering layer on the metal oxide layer; forming a first top electrode sub-layer on the oxygen atom gettering layer; forming a second top electrode sub-layer on the first top electrode sub-layer, wherein the first top electrode sub-layer and the second top electrode sub-layer comprise a top electrode; and subjecting the metal oxide layer and the oxygen atom gettering layer to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, resulting in a plurality of oxygen vacancies within the metal oxide layer.

Abstract translation: 提供了一种电阻随机存取存储器及其制造方法。 该方法包括在基板上形成底部电极; 在底部电极上形成金属氧化物层; 在所述金属氧化物层上形成氧原子吸气层; 在氧原子吸气层上形成第一顶电极子层; 在所述第一顶部电极子层上形成第二顶部电极子层，其中所述第一顶部电极子层和所述第二顶部电极子层包括顶部电极; 并且对金属氧化物层和氧原子吸气层进行热处理，驱动金属氧化物层的氧原子迁移到氧原子吸气层中并与氧原子吸气层反应，导致金属氧化物层内的多个氧空位 。

公开(公告)号：US20130105758A1

公开(公告)日：2013-05-02

申请号：US13719245

申请日：2012-12-19

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Heng-Yuan Lee ,  Pei-Yi Gu ,  Yu-Sheng Chen

IPC: H01L45/00

CPC classification number: H01L45/145 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1641

Abstract: A memory cell of a resistive random access memory and a manufacturing method thereof are provided. The method includes the following steps. A first electrode is formed. A metal oxide layer is formed on the first electrode. An electrode buffer stacked layer is formed on the metal oxide layer and includes a first buffer layer and a second buffer layer, and the first buffer layer is located between the second buffer layer and the metal oxide layer. An oxidation reaction between the second buffer layer and the metal oxide layer is relatively easier than an oxidation reaction between the first buffer layer and the metal oxide layer. A second electrode layer is formed on the electrode buffer stacked layer.

Abstract translation: 提供了一种电阻随机存取存储器的存储单元及其制造方法。 该方法包括以下步骤。 形成第一电极。 在第一电极上形成金属氧化物层。 电极缓冲层叠层形成在金属氧化物层上，具有第一缓冲层和第二缓冲层，第一缓冲层位于第二缓冲层和金属氧化物层之间。 第二缓冲层和金属氧化物层之间的氧化反应比第一缓冲层和金属氧化物层之间的氧化反应相对容易。 在电极缓冲层叠层上形成第二电极层。

公开(公告)号：US20210257017A1

公开(公告)日：2021-08-19

申请号：US16850016

申请日：2020-04-16

Applicant: Industrial Technology Research Institute

Inventor： Fu-Cheng Tsai ,  Heng-Yuan Lee ,  Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4099 ,  G11C11/56

Abstract: A computation operator in memory and an operation method thereof are provided. The computation operator in memory includes a word line calculator, a decision-maker and a sense amplifier. The word line calculator calculates a number of enabled word lines of a memory. The decision-maker generates a plurality of reference signals according to at least one of the number of enabled word lines and a used size of the memory, the reference signals are configured to set a distribution range. The sense amplifier receives a readout signal of the memory, and obtains a computation result by converting the readout signal according to the reference signals.

公开(公告)号：US20180342598A1

公开(公告)日：2018-11-29

申请号：US15790858

申请日：2017-10-23

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Kan-Hsueh Tsai ,  Heng-Yuan Lee

IPC: H01L29/66 ,  H01L29/20 ,  H01L21/02 ,  H01L29/778 ,  H01L29/205 ,  H01L21/285 ,  H01L29/45

CPC classification number: H01L29/66462 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/452 ,  H01L29/7787

Abstract: A GaN-based transistor device comprises a substrate; a buffer layer disposed on the substrate; a channel layer disposed on the buffer layer; a barrier layer disposed on a part of the channel layer; a passivation layer disposed on the barrier layer; wherein the barrier layer and the passivation layer comprise a first side wall and a second side wall; a barrier metal layer disposed on the passivation layer has a first opening that exposes a part of the passivation layer, and the passivation layer has a second opening located in the first opening; a gate electrode disposed on the exposed part of the barrier layer, a source electrode disposed on the channel layer covers the first side wall and a part of the barrier metal layer, and a drain electrode disposed on the channel layer covers the second side wall and another part of the barrier metal layer.

公开(公告)号：US20180211997A1

公开(公告)日：2018-07-26

申请号：US15453914

申请日：2017-03-09

Applicant: Industrial Technology Research Institute

Inventor： Yu-De Lin ,  Heng-Yuan Lee

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2427 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/146

Abstract: A structure of random access memory includes a memory cell and a selector. The memory cell has two different conductive states according to a bias applied on the memory cell. The selector is electrically connected to the memory cell in series. An operation voltage is applied between two end terminals of the memory cell and the selector connected in series. A structure of the selector formed from multiple capacitors coupled in series, includes a plurality of dielectric layers corresponding to the capacitors; and a metal conductive layer, disposed between the dielectric layers. A material of the metal conductive layer is to resist a material inter-diffusion between adjacent two of the dielectric layers in different materials.

公开(公告)号：US20150021542A1

公开(公告)日：2015-01-22

申请号：US14510135

申请日：2014-10-09

Applicant: Industrial Technology Research Institute

Inventor： Heng-Yuan Lee ,  Pei-Yi Gu ,  Yu-Sheng Chen

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L45/1233 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1641

Abstract: A memory cell of a resistive random access memory and a manufacturing method thereof are provided. The method includes the following steps. A first electrode is formed. A metal oxide layer is formed on the first electrode. An electrode buffer stacked layer is formed on the metal oxide layer and includes a first buffer layer and a second buffer layer, and the first buffer layer is located between the second buffer layer and the metal oxide layer. The second buffer layer reacts with oxygen from the first buffer layer more strongly than the first buffer layer reacts with oxygen from the metal oxide layer. A second electrode layer is formed on the electrode buffer stacked layer.

Abstract translation: 提供了一种电阻随机存取存储器的存储单元及其制造方法。 该方法包括以下步骤。 形成第一电极。 在第一电极上形成金属氧化物层。 电极缓冲层叠层形成在金属氧化物层上，具有第一缓冲层和第二缓冲层，第一缓冲层位于第二缓冲层和金属氧化物层之间。 第二缓冲层与第一缓冲层的氧比第一缓冲层与来自金属氧化物层的氧反应更加强烈。 在电极缓冲层叠层上形成第二电极层。

公开(公告)号：US11217661B2

公开(公告)日：2022-01-04

申请号：US16842589

申请日：2020-04-07

Applicant: Industrial Technology Research Institute

Inventor： Yu-De Lin ,  Heng-Yuan Lee ,  Po-Chun Yeh ,  Chih-Yao Wang ,  Hsin-Yun Yang

IPC: H01L49/02 ,  H01L27/11502 ,  H01L27/11507 ,  G11C11/22

Abstract: A ferroelectric memory is provided. The ferroelectric memory includes a substrate, a first conductive layer disposed on the substrate, a patterned oxide layer disposed on the first conductive layer and the substrate, exposing a part of the first conductive layer, a second conductive layer disposed on the exposed first conductive layer and the patterned oxide layer, an antiferroelectric layer disposed on the exposed first conductive layer and the second conductive layer, a ferroelectric layer disposed on the second conductive layer and located on the antiferroelectric layer, a conductive oxide layer disposed between the antiferroelectric layer, and a third conductive layer disposed on the conductive oxide layer and between the ferroelectric layer.

公开(公告)号：US20210150317A1

公开(公告)日：2021-05-20

申请号：US16809522

申请日：2020-03-04

Applicant: Industrial Technology Research Institute

Inventor： Tuo-Hung Hou ,  Shyh-Shyuan Sheu ,  Jeng-Hua Wei ,  Heng-Yuan Lee ,  Ming-Hung Wu

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08 ,  G11C13/00 ,  G11C11/16 ,  G11C11/54

Abstract: A neuron circuit and an artificial neural network chip are provided. The neuron circuit includes a memristor and an integrator. The memristor generates a pulse train having an oscillation frequency when an applied voltage exceeds a predetermined threshold. The integrator is connected in parallel to the memristor for receiving and accumulating input pulses transmitted by a previous layer network at different times, and driving the memristor to transmit the pulse train to a next layer network when a voltage of the accumulated input pulses exceeds the predetermined threshold.