公开(公告)号：US20140209904A1

公开(公告)日：2014-07-31

申请号：US13753636

申请日：2013-01-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Stefan Tegen ,  Marko Lemke

IPC: H01L21/66

CPC classification number: H01L22/30 ,  H01L22/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated test circuit, including a plurality of test structure elements, wherein each test structure element includes at least a supply line and a test line; a plurality of select transistors, wherein each select transistor is assigned to one corresponding test structure element, and wherein each select transistor includes a first controlled region, a second controlled region, and a control region, wherein the second controlled region of each select transistor is respectively connected to the supply line of the corresponding test structure element, so that each select transistor is unambiguously assigned to the corresponding test structure element; and a plurality of contact pads, connected to respective first controlled regions and control regions of the plurality of select transistors, such that each test structure element of the plurality of test structure elements can be individually addressed by the plurality of contact pads.

Abstract translation: 一种集成测试电路，包括多个测试结构元件，其中每个测试结构元件至少包括供电线和测试线; 多个选择晶体管，其中每个选择晶体管分配给一个对应的测试结构元件，并且其中每个选择晶体管包括第一受控区域，第二受控区域和控制区域，其中每个选择晶体管的第二受控区域是 分别连接到相应的测试结构元件的电源线，使得每个选择晶体管被明确地分配给相应的测试结构元件; 以及多个接触焊盘，连接到多个选择晶体管的相应的第一受控区域和控制区域，使得多个测试结构元件中的每个测试结构元件可以被多个接触焊盘单独寻址。

公开(公告)号：US10312159B2

公开(公告)日：2019-06-04

申请号：US15798972

申请日：2017-10-31

Applicant: Infineon Technologies AG

Inventor： Frank Hoffmann ,  Dirk Manger ,  Andreas Pribil ,  Marc Probst ,  Stefan Tegen

IPC: H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/737

Abstract: A method comprises providing a substrate of a first conductive type and a layer stack arranged on the substrate. The layer stack comprises a first isolation layer, a sacrificial layer, and a second isolation layer. The layer stack comprises a window formed in the layer stack through the second isolation layer, the sacrificial layer and the first isolation layer up to a surface region of the substrate. The method comprises providing a collector layer. The method comprises providing a base layer on the collector layer within the window of the layer stack. The method comprises providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack. The method further comprises selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer.

公开(公告)号：US09847326B2

公开(公告)日：2017-12-19

申请号：US14037429

申请日：2013-09-26

Applicant: Infineon Technologies AG

Inventor： Stefan Tegen ,  Marko Lemke

IPC: H01L27/01 ,  H01L21/822 ,  H01M6/40 ,  H01M10/04 ,  H01M10/42 ,  H01L49/02 ,  H01G4/33 ,  H01G4/40 ,  H01G11/08

CPC classification number: H01L27/016 ,  H01G4/33 ,  H01G4/40 ,  H01G11/08 ,  H01L21/822 ,  H01L28/00 ,  H01L28/90 ,  H01L2224/04105 ,  H01L2224/24195 ,  H01L2924/12044 ,  H01M6/40 ,  H01M10/0436 ,  H01M10/4257 ,  H01L2924/00

Abstract: According to various embodiments, an electronic structure may be provided, the electronic structure may include: a semiconductor carrier, and a battery structure monolithically integrated with the semiconductor carrier, the battery structure including a plurality of thin film batteries.

公开(公告)号：US20150084157A1

公开(公告)日：2015-03-26

申请号：US14037429

申请日：2013-09-26

Applicant: Infineon Technologies AG

Inventor： Stefan Tegen ,  Marko Lemke

IPC: H01L27/01 ,  H01L21/822

CPC classification number: H01L27/016 ,  H01G4/33 ,  H01G4/40 ,  H01G11/08 ,  H01L21/822 ,  H01L28/00 ,  H01L28/90 ,  H01L2224/04105 ,  H01L2224/24195 ,  H01L2924/12044 ,  H01M6/40 ,  H01M10/0436 ,  H01M10/4257 ,  H01L2924/00

Abstract: According to various embodiments, an electronic structure may be provided, the electronic structure may include: a semiconductor carrier, and a battery structure monolithically integrated with the semiconductor carrier, the battery structure including a plurality of thin film batteries.

Abstract translation: 根据各种实施例，可以提供电子结构，电子结构可以包括：半导体载体和与半导体载体单片集成的电池结构，该电池结构包括多个薄膜电池。