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    METHOD FOR MANUFACTURING A PLURALITY OF NANOWIRES
    1.
    发明申请
    METHOD FOR MANUFACTURING A PLURALITY OF NANOWIRES 审中-公开
    制造多种纳米尺寸的方法

    公开(公告)号：US20160111719A1

    公开(公告)日：2016-04-21

    申请号：US14977719

    申请日：2015-12-22

    Applicant: Infineon Technologies AG

    Inventor： Marko Lemke ,  Stefan Tegen ,  Uwe Rudolph

    IPC: H01M4/38 ,  H01M4/66 ,  H01M10/0525 ,  H01L29/06 ,  H01L29/16

    Abstract: A method for manufacturing a plurality of nanowires, the method including: providing a carrier comprising an exposed surface of a material to be processed and applying a plasma treatment on the exposed surface of the material to be processed to thereby form a plurality of nanowires from the material to be processed during the plasma treatment.

    Abstract translation: 一种用于制造多个纳米线的方法，所述方法包括：提供包括待处理材料的暴露表面的载体，并在待处理材料的暴露表面上施加等离子体处理，从而形成多个纳米线 在等离子体处理期间待处理的材料。

    INTEGRATED CIRCUIT STRUCTURE AND A BATTERY STRUCTURE
    4.
    发明申请
    INTEGRATED CIRCUIT STRUCTURE AND A BATTERY STRUCTURE 审中-公开
    集成电路结构和电池结构

    公开(公告)号：US20150086809A1

    公开(公告)日：2015-03-26

    申请号：US14037422

    申请日：2013-09-26

    Applicant: Infineon Technologies AG

    Inventor： Marko Lemke ,  Stefan Tegen

    IPC: H01M10/42 ,  H01M10/04

    CPC classification number: H01M10/425 ,  H01L23/50 ,  H01L2924/0002 ,  H01M10/0436 ,  H01M10/0525 ,  H01M10/0562 ,  H01L2924/00

    Abstract: According to various embodiments, an integrated circuit structure may include: an electronic circuit being arranged on a surface of a carrier, and a solid state electrolyte battery being at least partially arranged within the carrier, wherein at least a part of the solid state electrolyte battery being arranged within the carrier is overlapping with the electronic circuit along a direction parallel to the surface of the carrier.

    Abstract translation: 根据各种实施例，集成电路结构可以包括：电子电路布置在载体的表面上，固态电解质电池至少部分地布置在载体内，其中至少一部分固态电解质电池 布置在载体内的电子电路沿着与载体表面平行的方向重叠。

    Integrated test circuit and method for manufacturing an integrated test circuit
    8.
    发明授权
    Integrated test circuit and method for manufacturing an integrated test circuit 有权
    集成测试电路及制造集成测试电路的方法

    公开(公告)号：US09230870B2

    公开(公告)日：2016-01-05

    申请号：US13753636

    申请日：2013-01-30

    Applicant: Infineon Technologies AG

    Inventor： Stefan Tegen ,  Marko Lemke

    IPC: H01L29/10 ,  H01L21/00 ,  H01L21/66

    CPC classification number: H01L22/30 ,  H01L22/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated test circuit, including a plurality of test structure elements, wherein each test structure element includes at least a supply line and a test line; a plurality of select transistors, wherein each select transistor is assigned to one corresponding test structure element, and wherein each select transistor includes a first controlled region, a second controlled region, and a control region, wherein the second controlled region of each select transistor is respectively connected to the supply line of the corresponding test structure element, so that each select transistor is unambiguously assigned to the corresponding test structure element; and a plurality of contact pads, connected to respective first controlled regions and control regions of the plurality of select transistors, such that each test structure element of the plurality of test structure elements can be individually addressed by the plurality of contact pads.

    Abstract translation: 一种集成测试电路，包括多个测试结构元件，其中每个测试结构元件至少包括供电线和测试线; 多个选择晶体管，其中每个选择晶体管分配给一个对应的测试结构元件，并且其中每个选择晶体管包括第一受控区域，第二受控区域和控制区域，其中每个选择晶体管的第二受控区域是 分别连接到相应的测试结构元件的电源线，使得每个选择晶体管被明确地分配给相应的测试结构元件; 以及多个接触焊盘，连接到多个选择晶体管的相应的第一受控区域和控制区域，使得多个测试结构元件中的每个测试结构元件可以被多个接触焊盘单独寻址。

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