公开(公告)号：US09159620B2

公开(公告)日：2015-10-13

申请号：US14474482

申请日：2014-09-02

Applicant: Infineon Technologies AG

Inventor： Gunther Mackh ,  Uwe Seidel ,  Rainer Leuschner

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76898 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76877 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a substrate; forming a dielectric layer over the substrate; forming a first opening and a second opening at least partially simultaneously through the dielectric layer over the substrate; and forming a third opening through the bottom surface of the first opening and into at least a portion of the substrate.

Abstract translation: 一个或多个实施例涉及制造半导体结构的方法，包括：提供衬底; 在所述衬底上形成介电层; 形成第一开口和第二开口，所述第一开口和第二开口至少部分同时穿过所述基底上的介电层; 以及形成穿过所述第一开口的底表面并进入所述基底的至少一部分的第三开口。

公开(公告)号：US08815743B2

公开(公告)日：2014-08-26

申请号：US13830185

申请日：2013-03-14

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Uwe Hoeckele ,  Thomas Kunstmann ,  Uwe Seidel

IPC: H01L21/311

CPC classification number: H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming the through substrate via by filling an opening with a first fill material and depositing a first insulating layer over the first fill material, the first insulating layer not being deposited on sidewalls of the fill material in the opening, wherein sidewalls of the first insulating layer form a gap over the opening. The method further includes forming a void by sealing the opening using a second insulating layer.

Abstract translation: 描述了在形成半导体部件时通过衬底通孔形成的结构和方法。 在一个实施例中，本发明描述了一种通过用第一填充材料填充开口形成通孔基底通孔的方法，并且在第一填充材料上沉积第一绝缘层，第一绝缘层不被沉积在填充材料的侧壁上 所述开口，其中所述第一绝缘层的侧壁在所述开口上形成间隙。 该方法还包括通过使用第二绝缘层密封开口来形成空隙。

公开(公告)号：US20140127895A1

公开(公告)日：2014-05-08

申请号：US14153322

申请日：2014-01-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Gabriele Bettineschi ,  Uwe Seidel ,  Wolfgang Walter ,  Michael Schrenk ,  Hubert Werthmann

IPC: H01L21/768

CPC classification number: H01L21/76886 ,  H01L23/5256 ,  H01L2224/13

Abstract: A semiconductor device comprises a semiconductor substrate, an anorganic isolation layer on the semiconductor substrate and a metallization layer on the anorganic isolation layer. The metallization layer comprises a fuse structure. At least in an area of the fuse structure the metallization layer and the anorganic isolation layer have a common interface.

Abstract translation: 半导体器件包括半导体衬底，半导体衬底上的无机隔离层和有机隔离层上的金属化层。 金属化层包括熔丝结构。 至少在熔丝结构的区域中，金属化层和有机隔离层具有共同的界面。