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公开(公告)号：US20160373242A1
公开(公告)日：2016-12-22
申请号：US15252057
申请日：2016-08-30
Applicant: INPHI CORPORATION
Inventor： Parmanand MISHRA , Simon FOREY
CPC classification number: H04L7/0079 , H03K5/135 , H03K2005/00052 , H03L7/0807 , H04B1/10 , H04B1/40 , H04L7/033 , H04L7/0331 , H04L7/06 , H04L7/10
Abstract: The present invention is directed to data communication. More specifically, the present invention provides a mechanism for determining an adjustment delay that minimizes skew error due to poor alignment between edge samples and data samples. The adjustment delay is determined by sampling edge samples and data samples using different test delays at a calibration frequency that is different from the sampling frequency. The test delay associated with the least average position between the data samples and edge samples is selected as the adjustment delay. The adjustment delay is used as a parameter when sampling data at the sampling frequency. There are other embodiments as well.
Abstract translation: 本发明涉及数据通信。 更具体地，本发明提供了一种用于确定最小化由于边缘样本和数据样本之间的不良对准导致的偏斜误差的调整延迟的机制。 调整延迟由采样边缘样本和采样频率不同的不同测试延迟采样数据样本确定。 选择与数据样本和边缘样本之间的最小平均位置相关联的测试延迟作为调整延迟。 当以采样频率采样数据时，调整延迟用作参数。 还有其它实施例。
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Patent Agency Ranking
公开(公告)号：US20190044521A1
公开(公告)日：2019-02-07
申请号：US16154522
申请日：2018-10-08
Applicant: INPHI CORPORATION
Inventor： Simon FOREY , Rajasekhar NAGULAPALLI , Parmanand MISHRA
CPC classification number: H03L7/0807 , H03G3/20 , H03K5/1565 , H04L27/01
Abstract: Embodiments of the present invention provide techniques for duty cycle correction of clock signals. An input clock signal passes through a pair of output transistors, which provides an output clock signal based on the input clock signal. A duty cycle sensor generates a first correction signal based on the output clock signal. The first correction signal is at least partially opposite of the output clock signal. A duty cycle corrector generates a second correction signal based on the first correction signal. The duty cycle corrector includes two or more transistors for generating the second correction signal. The second correction signal is applied to the output clock signal. There are other embodiments as well.
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公开(公告)号：US20180294899A1
公开(公告)日：2018-10-11
申请号：US15995042
申请日：2018-05-31
Applicant: INPHI CORPORATION
Inventor： Simon FOREY , Rajasekhar NAGULAPALLI , Parmanand MISHRA , Michael S. HARWOOD
IPC: H04B17/21 , H04B17/318 , H04L12/26 , H03K5/19 , H03K3/3565
CPC classification number: H04B17/21 , H03K3/3565 , H03K5/19 , H04B17/318
Abstract: The present invention is directed to data communication. According to a specific embodiment, the present invention provides technique for loss of signal detection. A loss-of-signal detection (LOSD) device determines an analog signal indicating signal strength by subtracting a threshold offset voltage from an incoming signal. The analog signal is then processed by a switch network of an output stage circuit, which provides a digital output of loss of signal indication at a low frequency (relative to the incoming signal frequency). There are other embodiments as well.
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公开(公告)号：US20180183444A1
公开(公告)日：2018-06-28
申请号：US15840984
申请日：2017-12-13
Applicant: INPHI CORPORATION
Inventor： Simon FOREY , Rajasekhar NAGULAPALLI , Parmanand MISHRA
CPC classification number: H03L7/0807 , H03G3/20 , H03K5/1565 , H04L27/01
Abstract: Embodiments of the present invention provide techniques for duty cycle correction of clock signals. An input clock signal passes through a pair of output transistors, which provides an output clock signal based on the input clock signal. A duty cycle sensor generates a first correction signal based on the output clock signal. The first correction signal is at least partially opposite of the output clock signal. A duty cycle corrector generates a second correction signal based on the first correction signal. The duty cycle corrector includes two or more transistors for generating the second correction signal. The second correction signal is applied to the output clock signal. There are other embodiments as well.
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公开(公告)号：US20170163408A1
公开(公告)日：2017-06-08
申请号：US15433601
申请日：2017-02-15
Applicant: INPHI CORPORATION
Inventor： Simon FOREY , Parmanand MISHRA , Sean BATTY
CPC classification number: H04L7/0087 , H03M9/00 , H04B10/6164 , H04L7/0004 , H04L7/0331 , H04L7/06 , H04L27/152
Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a method for acquiring sampling frequency by sweeping through a predetermined frequency range, performing data sampling at different frequencies within the predetermined frequency range, and determining a target frequency for sampling data based on a maximum early peak frequency and a maximum late peak frequency. There are other embodiments as well.
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公开(公告)号：US20170019119A1
公开(公告)日：2017-01-19
申请号：US15277076
申请日：2016-09-27
Applicant: INPHI CORPORATION
Inventor： Parmanand MISHRA , Simon FOREY
CPC classification number: H03M1/1023 , H03M1/66 , H04L25/03057 , H04L25/03878
Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide an offset correction technique for a SERDES system. A CTLE module for receiving input data signal is set to an isolation mode, and one or more sense amplifiers perform data sampling asynchronously during the isolation mode. During the isolation mode, CLTE(s) that are not directly connected to the sense amplifiers are shut. Data sampled during the isolation mode are used to determine an offset value that is later used in normal operation of the SERDES system. There are other embodiments as well.
Abstract translation: 本发明涉及数据通信。 更具体地，本发明的实施例提供了一种用于SERDES系统的偏移校正技术。 用于接收输入数据信号的CTLE模块被设置为隔离模式，并且一个或多个感测放大器在隔离模式期间异步地进行数据采样。 在隔离模式下，不直接连接到读出放大器的CLTE被关闭。 在隔离模式下采样的数据用于确定稍后在SERDES系统的正常操作中使用的偏移值。 还有其它实施例。
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