公开(公告)号：US20160179586A1

公开(公告)日：2016-06-23

申请号：US14574300

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Cheng Wang ,  Youfeng Wu ,  Sara S. Baghsorkhi ,  Albert Hartono ,  Robert Valentine

IPC: G06F9/52 ,  G06F12/08

CPC classification number: G06F9/528 ,  G06F8/41 ,  G06F8/4451 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3863 ,  G06F12/0828 ,  G06F12/0875 ,  G06F2212/452

Abstract: Embodiments described herein utilize restricted transactional memory (RTM) instructions to implement speculative compile time optimizations that will be automatically rolled back by hardware in the event of a missed speculation. In one embodiment, a lightweight version of RTM for speculative compiler optimization is described to provide lower operational overhead in comparison to conventional RTM implementations used when performing SLE.

Abstract translation: 本文描述的实施例使用受限制的事务存储器（RTM）指令来实现推测性的编译时间优化，其将在错误的猜测的情况下被硬件自动地回滚。 在一个实施例中，与用于执行SLE的常规RTM实现相比，描述了用于推测性编译器优化的轻量级RTM以提供较低的操作开销。

公开(公告)号：US09244677B2

公开(公告)日：2016-01-26

申请号：US13630147

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Nalini Vasudevan ,  Jayashankar Bharadwaj ,  Christopher J. Hughes ,  Milind B. Girkar ,  Mark J Charney ,  Robert Valentine ,  Victor W. Lee ,  Daehyun Kim ,  Albert Hartono ,  Sara S. Baghsorkhi

IPC: G06F9/44 ,  G06F9/38 ,  G06F9/45

CPC classification number: G06F8/443 ,  G06F8/433 ,  G06F8/452 ,  G06F8/70 ,  G06F9/30036 ,  G06F9/38 ,  G06F9/3836

Abstract: Loop vectorization methods and apparatus are disclosed. An example method includes setting a dynamic adjustment value of a vectorization loop; executing the vectorization loop to vectorize a loop by grouping iterations of the loop into one or more vectors; identifying a dependency between iterations of the loop as; and setting the dynamic adjustment value based on the identified dependency.

Abstract translation: 公开了环向量化方法和装置。 示例性方法包括设置矢量化循环的动态调整值; 执行向量化循环以通过将循环的迭代分组为一个或多个向量来矢量化循环; 识别循环迭代之间的依赖关系; 并且基于所识别的依赖关系来设置动态调整值。

公开(公告)号：US10402177B2

公开(公告)日：2019-09-03

申请号：US15660603

申请日：2017-07-26

Applicant: Intel Corporation

Inventor： Jayashankar Bharadwaj ,  Nalini Vasudevan ,  Albert Hartono ,  Sara S. Baghsorkhi

IPC: G06F9/45 ,  G06F8/41 ,  G06F9/06 ,  G06F9/30 ,  G06F9/44

Abstract: Methods and systems to convert a scalar computer program loop having loop-carried dependences into a vector computer program loop are disclosed. One such method includes, at runtime, identifying, by executing an instruction with one or more processors, a first loop iteration that cannot be executed in parallel with a second loop iteration due to a set of conflicting scalar loop operations. The first loop iteration is executed after the second loop iteration. The method also includes sectioning, by executing an instruction with one or more processors, a vector loop into vector partitions including a first vector partition. The first vector partition executes consecutive loop iterations in parallel and the consecutive loop iterations start at the second loop iteration and end before the first loop iteration.

公开(公告)号：US10372450B2

公开(公告)日：2019-08-06

申请号：US15647123

申请日：2017-07-11

Applicant: Intel Corporation

Inventor： Victor W. Lee ,  Daehyun Kim ,  Tin-Fook Ngai ,  Jayashankar Bharadwaj ,  Albert Hartono ,  Sara Baghsorkhi ,  Nalini Vasudevan

IPC: G06F9/302 ,  G06F9/305 ,  G06F9/315 ,  G06F15/76 ,  G06F9/30 ,  G06F15/80

Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction are described.

公开(公告)号：US10324768B2

公开(公告)日：2019-06-18

申请号：US14574300

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Cheng Wang ,  Youfeng Wu ,  Sara S. Baghsorkhi ,  Albert Hartono ,  Robert Valentine

IPC: G06F9/30 ,  G06F9/52 ,  G06F12/0875 ,  G06F12/0817

Abstract: Embodiments described herein utilize restricted transactional memory (RTM) instructions to implement speculative compile time optimizations that will be automatically rolled back by hardware in the event of a missed speculation. In one embodiment, a lightweight version of RTM for speculative compiler optimization is described to provide lower operational overhead in comparison to conventional RTM implementations used when performing SLE.

公开(公告)号：US20160139897A1

公开(公告)日：2016-05-19

申请号：US15005781

申请日：2016-01-25

Applicant: Intel Corporation

Inventor： Nalini Vasudevan ,  Jayashankar Bharadwaj ,  Christopher J. Hughes ,  Milind B. Girkar ,  Mark J. Charney ,  Robert Valentine ,  Victor W. Lee ,  Daehyun Kim ,  Albert Hartono ,  Sara S. Baghsorkhi

IPC: G06F9/45

CPC classification number: G06F8/443 ,  G06F8/433 ,  G06F8/452 ,  G06F8/70 ,  G06F9/30036 ,  G06F9/38 ,  G06F9/3836

Abstract: Loop vectorization methods and apparatus are disclosed. An example method includes prior to executing an original loop having iterations, analyzing, via a processor, the iterations of the original loop, identifying a dependency between a first one of the iterations of the original loop and a second one of the iterations of the original loop, after identifying the dependency, vectorizing a first group of the iterations of the original loop based on the identified dependency to form a vectorization loop, and setting a dynamic adjustment value of the vectorization loop based on the identified dependency.

Abstract translation: 公开了环向量化方法和装置。 示例性方法包括在执行具有迭代的原始循环之前，经由处理器分析原始循环的迭代，识别原始循环的第一迭代和原始循环的第二迭代之间的依赖关系 循环，在识别依赖性之后，基于所识别的依赖关系对原始循环的第一组迭代进行矢量化以形成矢量化循环，以及基于所识别的依赖关系来设置矢量化循环的动态调整值。

公开(公告)号：US09268541B2

公开(公告)日：2016-02-23

申请号：US13994062

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Jayashankar Bharadwaj ,  Nalini Vasudevan ,  Albert Hartono ,  Sara S. Baghsorkhi

IPC: G06F9/45 ,  G06F9/06 ,  G06F9/30 ,  G06F9/44

CPC classification number: G06F8/4441 ,  G06F8/443 ,  G06F8/452 ,  G06F9/06 ,  G06F9/30 ,  G06F9/44

Abstract: Methods and systems to convert scalar computer program loops having loop carried dependences to vector computer program loops are disclosed. One example method and system generates a first predicate set associated with a first conditionally executed statement. The first predicate set contains a first set of predicates that cause a variable to be defined in a scalar computer program loop at or before the variable is defined by the first conditionally executed statement. The method and system also generates a second predicate set associated with the first conditionally executed statement. The second predicate set contains a second set of predicates that cause the variable to be used in the scalar computer program loop at or before the variable is defined by the first conditionally executed statement. The method and system determines whether the second predicate set is a subset of the first predicate set and, based on the determination, propagates a vector value in an element of a vector of the variable to a subsequent element of the vector.

Abstract translation: 公开了将具有循环携带依赖性的标量计算机程序循环转换为向量计算机程序循环的方法和系统。 一个示例性方法和系统生成与第一条件执行语句相关联的第一谓词集合。 第一个谓词集包含第一组谓词，导致在第一个有条件执行的语句定义变量之前或之前，在标量计算机程序循环中定义变量。 方法和系统还生成与第一条件执行语句相关联的第二谓词集合。 第二个谓词集包含第二组谓词，导致在第一个有条件执行的语句定义变量之前或之前在标量计算机程序循环中使用变量。 方法和系统确定第二谓词集是否是第一谓词集的子集，并且基于该确定，将该变量的向量的元素中的向量值传播到向量的后续元素。

公开(公告)号：US20140237303A1

公开(公告)日：2014-08-21

申请号：US13997664

申请日：2011-12-23

Applicant: INTEL CORPORATION

Inventor： Jayashankar Bharadwaj ,  Victor W. Lee ,  Kim Daehyun ,  Nalini Vasudevan ,  Tin-Fook Ngai ,  Albert Hartono ,  Sara S. Baghsorkhi

IPC: G06F11/07

CPC classification number: G06F11/0751 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043

Abstract: An apparatus and method are described for detecting and responding to fault conditions in a processor. For example, one embodiment of a method comprises: reading each active element in succession from a first vector register, each active element specifying an address for a gather or load operation; detecting one or more fault conditions associated with one or more of the active elements; for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing the data loaded from an address associated with the active element in a first output vector register; and for each active element associated with the detected fault condition and following the detected fault condition, setting a bit in an output mask register to indicate the detected fault condition.

Abstract translation: 描述了用于检测和响应处理器中的故障状况的装置和方法。 例如，一种方法的一个实施例包括：从第一向量寄存器连续读取每个有源元件，每个有源元件指定用于集合或加载操作的地址; 检测与一个或多个所述有源元件相关联的一个或多个故障状况; 对于在除了所述第一有源元件之外的元件的检测到的故障状况之前连续读取的每个有源元件，将从与所述有源元件相关联的地址加载的数据存储在第一输出向量寄存器中; 并且对于与检测到的故障状况相关联的每个有源元件并且跟随检测到的故障状况，设置输出屏蔽寄存器中的位以指示检测到的故障状况。