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    Apparatus and Method for Reducing Latency Between Host and a Storage Device
    11.
    发明申请
    Apparatus and Method for Reducing Latency Between Host and a Storage Device 审中-公开
    用于减少主机和存储设备之间的延迟的装置和方法

    公开(公告)号：US20160162416A1

    公开(公告)日：2016-06-09

    申请号：US14564035

    申请日：2014-12-08

    Applicant: Intel Corporation

    Inventor： James A. Boyd ,  Anand S. Ramalingam ,  Pallav H. Gala ,  John W. Carroll ,  Richard P. Mangold

    IPC: G06F12/10 ,  G06F13/28

    CPC classification number: G06F13/28 ,  G06F12/0246 ,  G06F2212/7201 ,  Y02D10/13 ,  Y02D10/14

    Abstract: Described is a system comprising: a storage device; a bus; and a host apparatus including a host memory and a driver module, wherein the host apparatus is coupled to the storage device via the bus, wherein the driver module is operable to: retrieve a logical to physical address mapping from the host memory; and provide the logical to physical address mapping to the storage device via the bus along with a read or write operation request. Described is a method comprising: retrieving a logical to physical address mapping from a host memory; and providing the logical to physical address mapping to a storage device via a bus along with a read or write operation request. Described is a machine readable storage medium having instructions stored thereon that, when executed, cause a machine to perform the method described above.

    Abstract translation: 描述了一种系统，包括：存储装置; 一辆公交车; 以及主机设备，包括主机存储器和驱动器模块，其中所述主机设备经由总线耦合到所述存储设备，其中所述驱动器模块可操作以：从所述主机存储器检索逻辑到物理地址映射; 并且通过总线提供与物理地址映射到存储设备的逻辑，以及读或写操作请求。 描述了一种方法，包括：从主机存储器检索逻辑到物理地址映射; 并且通过总线以及读或写操作请求将物理地址映射到物理地址映射到存储设备。 描述了一种其上存储有指令的机器可读存储介质，当被执行时，使机器执行上述方法。

    Adaptive write acknowledgment for storage devices
    12.
    发明授权
    Adaptive write acknowledgment for storage devices 有权

    公开(公告)号：US11210130B2

    公开(公告)日：2021-12-28

    申请号：US16855139

    申请日：2020-04-22

    Applicant: Intel Corporation

    Inventor： Bishwajit Dutta ,  Sanjeev N. Trika ,  Anand S. Ramalingam ,  Pallav H. Gala

    IPC: G06F9/46 ,  G06F3/06 ,  G06F9/54 ,  G06F9/48

    Abstract: Examples include techniques for managing high priority (HP) and low priority (LP) write transaction requests by a storage device. An embodiment includes receiving, at a storage controller for a storage device, a write transaction request from a requestor to write data to one or more memory devices in the storage device. When the write transaction request is for a high priority (HP) write, coalescing the write data into a transaction buffer in a memory of the storage device, sending an acknowledgment for the write transaction request to the requestor, and writing the write data into the one or more memory devices. When the write transaction request is for a low priority (LP) write, writing the write data into the one or more memory devices, and then sending an acknowledgment for the write transaction request to the requestor.

    Technologies for combining logical-to-physical address table updates in a single write operation
    13.
    发明授权
    Technologies for combining logical-to-physical address table updates in a single write operation 有权

    公开(公告)号：US10528463B2

    公开(公告)日：2020-01-07

    申请号：US15278837

    申请日：2016-09-28

    Applicant: Intel Corporation

    Inventor： Peng Li ,  Anand S. Ramalingam ,  William K. Lui ,  Sanjeev N. Trika

    IPC: G06F12/02 ,  G06F3/06 ,  G11C14/00

    Abstract: Technologies for combining logical-to-physical address updates include a data storage device. The data storage device includes a non-volatile memory to store data and a logical to physical (L2P) table indicative of logical addresses and associated physical addresses of the data. Additionally, the data storage device includes a volatile memory to store one or more bins. Each bin is indicative of a subset of entries in the L2P table. Further, the data storage device includes a controller to allocate a bin in the volatile memory, write a plurality of updates to a subset of entries of the L2P table to the bin, and write the bin to the L2P table in a single write operation. Other embodiments are also described and claimed.

    ACHIEVING CONSISTENT READ TIMES IN MULTI-LEVEL NON-VOLATILE MEMORY
    14.
    发明申请
    ACHIEVING CONSISTENT READ TIMES IN MULTI-LEVEL NON-VOLATILE MEMORY 审中-公开

    公开(公告)号：US20190332277A1

    公开(公告)日：2019-10-31

    申请号：US16376283

    申请日：2019-04-05

    Applicant: Intel Corporation

    Inventor： Anand S. Ramalingam ,  Pranav Kalavade

    IPC: G06F3/06 ,  G06F12/02

    Abstract: Systems, apparatuses and methods may provide for technology that reads a lower page, one or more intermediate pages and a last page from a set of multi-level non-volatile memory (NVM) cells, wherein one or more of a lower read time associated with the lower page or a last read time associated with the last page is substantially similar to an intermediate read time associated with the one or more intermediate pages.

    Managing solid state drive defect redundancies at sub-block granularity
    15.
    发明授权
    Managing solid state drive defect redundancies at sub-block granularity 有权

    公开(公告)号：US10275156B2

    公开(公告)日：2019-04-30

    申请号：US15280725

    申请日：2016-09-29

    Applicant: Intel Corporation

    Inventor： Anand S. Ramalingam ,  Jawad B. Khan ,  Pranav Kalavade

    IPC: G06F3/06 ,  G11C16/16 ,  G11C16/34 ,  G11C16/04

    Abstract: Systems, apparatuses and methods may provide for initiating an erase of a block of non-volatile memory in response to an erase command, wherein the block includes a plurality of sub-blocks. Additionally, a failure of the erase with respect to a first subset of the plurality of sub-blocks may be tracked on an individual sub-block basis, wherein the erase is successful with respect to a second subset of the plurality of sub-blocks. In one example, use of the second subset of the plurality of sub-blocks is permitted, whereas use of the first subset of the plurality of sub-blocks is prevented.

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