公开(公告)号：US20230044991A1

公开(公告)日：2023-02-09

申请号：US17393877

申请日：2021-08-04

Applicant: Intel Corporation

Inventor： Shantanu Rajwade ,  Kartik Ganapathi ,  Rohit Shenoy ,  Kristopher Gaewsky ,  MarkAnthony Golez ,  Vivek Angoth ,  Pranav Kalavade ,  Sarvesh Gangadhar

IPC: G06F3/06

Abstract: Systems, apparatuses and methods may provide for technology that detects a request to program a NAND memory containing a plurality of dies and programs the NAND memory on a stripe-by-stripe basis, wherein each stripe spans the plurality of dies and includes multiple types of pages. The multiple types of pages may reduce program time variability across the stripes and reduce the error susceptibility of the NAND memory.

公开(公告)号：US10454495B2

公开(公告)日：2019-10-22

申请号：US14490307

申请日：2014-09-18

Applicant: Intel Corporation

Inventor： Ravi H. Motwani ,  Pranav Kalavade

IPC: G06F9/38 ,  H03M7/02 ,  H03M5/16 ,  G06F3/00

Abstract: Described is an apparatus for converting binary data to ternary and back such that the apparatus comprises: a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits; and a first logic to receive a binary input and to convert the binary input to a ternary output according to the first LUT.

公开(公告)号：US09819362B2

公开(公告)日：2017-11-14

申请号：US14671140

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Ravi H. Motwani ,  Pranav Kalavade

IPC: H03M13/15 ,  H03M13/11 ,  G06F11/10 ,  G11C29/02 ,  G11C29/42 ,  G11C29/52 ,  G11C7/10 ,  G11C16/04 ,  G11C29/12

CPC classification number: H03M13/1515 ,  G06F11/1012 ,  G06F11/1024 ,  G06F11/1068 ,  G11C7/1006 ,  G11C16/0483 ,  G11C29/025 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/1204 ,  H03M13/1102

Abstract: Described is a method which comprises performing a first read from a portion of a non-volatile memory, the first read to provide a first codeword; decoding the first codeword; determining whether the decoding operation failed; performing a second read from the portion of the non-volatile memory when it is determined that the decoding operation failed, the second read to provide a second codeword; and decoding the second codeword with an errors-and-erasures decoding process.

公开(公告)号：US20170186497A1

公开(公告)日：2017-06-29

申请号：US14998119

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade

IPC: G11C29/38 ,  G11C29/44 ,  G11C5/14

CPC classification number: G11C29/38 ,  G11C5/148 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/44

Abstract: Methods and apparatus related to predictive Count Fail Byte (CFBYTE) for non-volatile memory are described. In one embodiment, logic determines a number of memory cells of the non-volatile memory that would pass or fail verification in a current program loop. The logic determines the number of the memory cells based at least in part on information from a previous program loop. The previous program loop is executed prior to the current program loop. The logic causes inhibition of one or more verification pulses to be issued in the current program loop based on comparison of the information from the previous program loop and a threshold value. Other embodiments are also disclosed and claimed.

公开(公告)号：US09535777B2

公开(公告)日：2017-01-03

申请号：US14087282

申请日：2013-11-22

Applicant: Intel Corporation

Inventor： Pranav Kalavade ,  Feng Zhu ,  Shyam Sunder Raghunathan ,  Ravi H. Motwani

IPC: G06F11/00 ,  G11C29/00 ,  G06F11/07 ,  G11B20/18

CPC classification number: G06F11/0751 ,  G06F11/073 ,  G06F11/1012 ,  G11B20/1816

Abstract: Systems and methods of managing defects in nonvolatile storage systems that can be used to avoid an inadvertent loss of data, while maintaining as much useful memory in the nonvolatile storage systems as possible. The disclosed systems and methods can monitor a plurality of trigger events for detecting possible defects in one or more nonvolatile memory (NVM) devices included in the nonvolatile storage systems, and apply one or more defect management policies to the respective NVM devices based on the types of trigger events that resulted in detection of the possible defects. Such defect management policies can be used proactively to retire memory in the nonvolatile storage systems with increased granularity, focusing the retirement of memory on regions of nonvolatile memory that are likely to contain a defect.

Abstract translation: 管理非易失性存储系统中的缺陷的系统和方法，可用于避免无意中丢失数据，同时尽可能保持非易失性存储系统中有用的内存。 所公开的系统和方法可以监视多个触发事件，用于检测非易失性存储系统中包括的一个或多个非易失性存储器（NVM）设备中的可能缺陷，并且基于类型向相应的NVM设备应用一个或多个缺陷管理策略 的触发事件导致检测到可能的缺陷。 可以主动地使用这种缺陷管理策略来以更小的粒度来在非易失性存储系统中退出内存，将存储器的退出重点集中在可能包含缺陷的非易失性存储器的区域上。

公开(公告)号：US12243590B2

公开(公告)日：2025-03-04

申请号：US17528892

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Christian Mion ,  Pranav Kalavade ,  Rohit S. Shenoy ,  Xin Sun ,  Kristopher Gaewsky

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56

Abstract: In one embodiment, an apparatus comprises a memory comprising a group of memory cells coupled to a wordline; and a controller configured to skip programming of one or more pages of the group of memory cells responsive to a sequential write operation; and program the one or more pages of the group of memory cells responsive to one or more random write commands.

公开(公告)号：US12224019B2

公开(公告)日：2025-02-11

申请号：US17213150

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Xiang Yang ,  Ali Khakifirooz ,  Pranav Kalavade ,  Shantanu R. Rajwade

IPC: G11C16/00 ,  G11C7/10 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

Abstract: A method, a memory chip controller of a flash memory device, and a flash memory device. The memory chip controller includes processing circuitry to receive data for a first page of N pages of data; and program cells of a memory location of the device to an nth threshold voltage level Ln, Ln corresponding to a program verify voltage level PVn, n being an integer from 0 to 2N−1, and Ln being one of 2N threshold voltage levels achievable using the N pages of data. Programming the cells includes: programming the cells based on the data for the first page while receiving data for subsequent pages of the N pages; and programming the cells based on the data for the subsequent pages, wherein programming the cells includes, for at least n=1, causing a respective dynamic start voltage (DSV) to be applied to the cells based on each respective page number p of the N pages for which data is received at the memory chip controller for the memory location to achieve PV1.

公开(公告)号：US20220310160A1

公开(公告)日：2022-09-29

申请号：US17212792

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Ali Khakifirooz ,  Pranav Kalavade ,  Shantanu Rajwade ,  Tarek Ahmed Ameen Beshari

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/24 ,  G06F3/06

Abstract: Systems, apparatuses and methods may provide for technology that boosts strings of a plurality of NAND sub-blocks to a pass voltage, deboosts a first subset of the boosted strings based on data associated with the plurality of NAND sub-blocks, and simultaneously programs the first subset while a second subset of the boosted strings remain at the pass voltage. In one example, to boost the strings of the NAND sub-blocks, the technology applies the pass voltage to selected and unselected wordlines that are connected to the NAND sub-blocks while selected and unselected strings are disconnected from a bitline that receives the data associated with the NAND sub-blocks.

公开(公告)号：US10599515B2

公开(公告)日：2020-03-24

申请号：US15851596

申请日：2017-12-21

Applicant: INTEL CORPORATION

Inventor： Pranav Kalavade ,  Ravi H. Motwani

IPC: G06F11/10 ,  H03M13/11 ,  G11C29/52 ,  G11C29/04

Abstract: A non-volatile memory unit receives a request from a controller to read encoded data stored in a non-volatile memory of the non-volatile memory unit. In response to determining by logic included in the non-volatile memory unit that the controller is estimated to be able to successfully decode the encoded data more than a predetermined percentage of times, the encoded data is transferred from the non-volatile memory unit to the controller.

公开(公告)号：US10438656B2

公开(公告)日：2019-10-08

申请号：US15845500

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Bharat M. Pathak ,  Binh N. Ngo ,  Naveen Vittal Prabhu ,  Karthikeyan Ramamurthi ,  Pranav Kalavade

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/08 ,  G11C8/08 ,  G11C16/32

Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.