公开(公告)号：US10956323B2

公开(公告)日：2021-03-23

申请号：US15976795

申请日：2018-05-10

Applicant: Intel Corporation

Inventor： Dale J. Juenemann ,  James A. Boyd ,  Robert J. Royer, Jr.

IPC: G06F12/08 ,  G06F12/0804 ,  G06F3/06

Abstract: Examples include techniques for emulating a non-volatile dual inline memory module (NVDIMM) in a computing platform using a non-volatile storage device. When a power up event occurs for the computing platform, a host memory buffer may be allocated in a system memory device and a backing store for the host memory buffer may be copied from the non-volatile storage device to the host memory buffer in the system memory device. When a power down event or a flush event occurs for the computing platform, the host memory buffer may be copied from the system memory device to the corresponding backing store for the host memory buffer in the non-volatile storage device. Thus, virtual NVDIMM functionality may be provided without having NVDIMM hardware in the computing platform.

公开(公告)号：US20190026226A1

公开(公告)日：2019-01-24

申请号：US15658177

申请日：2017-07-24

Applicant: Intel Corporation

Inventor： James A. Boyd ,  Dale J. Juenemann

IPC: G06F12/0877 ,  G06F12/0891 ,  G06F13/40 ,  G06F13/16

Abstract: A disclosed example to manage intermittently connectable storage media includes a cache initializer to initialize a nonvolatile cache corresponding to an intermittently connectable storage media device connected to a host system; a cache flush manager to change a cache flush mode associated with the nonvolatile cache from a cache write through mode to a cache write back mode based on the intermittently connectable storage media device being disconnected from the host system; a cache access manager to maintain the nonvolatile cache after the intermittently connectable storage media device is disconnected, and in response to a data access request corresponding to the intermittently connectable storage media device, perform a corresponding data access operation using the nonvolatile cache.

公开(公告)号：US20210089225A1

公开(公告)日：2021-03-25

申请号：US16952819

申请日：2020-11-19

Applicant: Intel Corporation

Inventor： James A. Boyd

IPC: G06F3/06

Abstract: Examples described herein relate to a device comprising a controller, a volatile memory device, and a non-volatile memory device. In some examples, the controller is to allocate an amount of the volatile memory device based on an amount of energy available to the device during a failure event. In some examples, the amount of energy available to the device during a failure event comprises watts over an amount of time. In some examples, the failure event comprises one or more of: power reduction, power loss, voltage reduction or loss, current reduction or loss, global reset, machine check, operating system (OS) failure or crash. In some examples, the allocated amount of the volatile memory device comprises a number of bytes. In some examples, the controller is to: indicate an amount of energy to copy data from the volatile memory device to the non-volatile memory device and receive an indication of the amount of energy available to the volatile memory device for a failure event.

公开(公告)号：US10482010B2

公开(公告)日：2019-11-19

申请号：US15637516

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： James A. Boyd ,  John W. Carroll ,  Sanjeev N. Trika

IPC: G11C7/10 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16

Abstract: An embodiment of a memory apparatus may include a persistent host memory buffer, and a memory controller communicatively coupled to the persistent host memory buffer to control communication between the persistent host memory buffer and a persistent storage media device. Other embodiments are disclosed and claimed.

公开(公告)号：US20190004940A1

公开(公告)日：2019-01-03

申请号：US15637516

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： James A. Boyd ,  John W. Carroll ,  Sanjeev N. Trika

IPC: G06F12/02 ,  G06F13/16 ,  G11C7/10 ,  G06F12/06

CPC classification number: G06F12/0246 ,  G06F12/0623 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/1694 ,  G06F2212/1024 ,  G06F2212/7203 ,  G11C7/1006

Abstract: An embodiment of a memory apparatus may include a persistent host memory buffer, and a memory controller communicatively coupled to the persistent host memory buffer to control communication between the persistent host memory buffer and a persistent storage media device. Other embodiments are disclosed and claimed.

公开(公告)号：US20160217069A1

公开(公告)日：2016-07-28

申请号：US15004162

申请日：2016-01-22

Applicant: Intel Corporation

Inventor： James A. Boyd ,  Dale J. Juenemann ,  Francis R. Corrado

IPC: G06F12/02 ,  G06F12/12 ,  G06F12/08

CPC classification number: G06F12/0246 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/12 ,  G06F2212/205 ,  G06F2212/217 ,  G06F2212/222 ,  G06F2212/60

Abstract: A host based caching technique may be used to determine caching policies for a hybrid hard disk drive. Because the host based caching may make use of knowledge about what data is being cached, improved performance may be achieved in some cases.

公开(公告)号：US10949356B2

公开(公告)日：2021-03-16

申请号：US16442267

申请日：2019-06-14

Applicant: Intel Corporation

Inventor： James A. Boyd ,  Robert J. Royer, Jr. ,  Lily P. Looi ,  Gary C. Chow ,  Zvika Greenfield ,  Chia-Hung S. Kuo ,  Dale J. Juenemann

IPC: G06F12/1009 ,  G06F12/1027

Abstract: A method is described. The method includes receiving notice of a page fault. A page targeted by a memory access instruction that resulted in the page fault residing in persistent memory without system memory status. In response to the page fault, updating page table information to include a translation that points to the page in persistent memory such that the page changes to system memory status without moving the page and system memory expands to include the page in persistent memory.

公开(公告)号：US10540505B2

公开(公告)日：2020-01-21

申请号：US15721554

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： James A. Boyd ,  Dale J. Juenemann ,  Robert J. Royer, Jr.

IPC: G06F11/30 ,  G06F21/60 ,  G06F3/06 ,  G06F16/27

Abstract: Technologies for protecting data in an asymmetric volume (ASV) that includes a first storage device that supports device-based encryption and a second storage device that does not support device-based encryption. In embodiments the technologies enable disparate capabilities of the storage devices in an ASV to be exposed to a user. When a complete copy of targeted data identified by a user input for encrypted storage is not present on the first storage device, at least a portion of the targeted data stored on the second storage device is rewritten to the first storage device. When a complete copy of the targeted data is stored on the first storage device, one or more security operations are performed to obfuscate or erase any portion of the targeted data stored on the second storage device.

公开(公告)号：US10204039B2

公开(公告)日：2019-02-12

申请号：US15004162

申请日：2016-01-22

Applicant: Intel Corporation

Inventor： James A. Boyd ,  Dale J. Juenemann ,  Francis R. Corrado

IPC: G06F12/02 ,  G06F12/0868 ,  G06F12/0804 ,  G06F12/12

Abstract: A host based caching technique may be used to determine caching policies for a hybrid hard disk drive. Because the host based caching may make use of knowledge about what data is being cached, improved performance may be achieved in some cases.

公开(公告)号：US20170371785A1

公开(公告)日：2017-12-28

申请号：US15195783

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： James A. Boyd ,  John W. Carroll ,  Sanjeev N. Trika ,  Mark A. Schmisseur

IPC: G06F12/0804

CPC classification number: G06F12/0804 ,  G06F12/0868 ,  G06F13/16 ,  G06F2212/1024 ,  G06F2212/7203 ,  Y02D10/13 ,  Y02D10/14

Abstract: Examples include techniques for a write commands to one or more storage devices coupled with a host computing platform. In some examples, the write commands may be responsive to write requests from applications hosted or supported by the host computing platform. A tracking table is utilized by elements of the host computing platform and the one or more storage devices such that the write commands are completed by the one or more storage devices without a need for an interrupt response to elements of the host computing platform.