公开(公告)号：US20160314826A1

公开(公告)日：2016-10-27

申请号：US14696050

申请日：2015-04-24

Applicant: INTEL CORPORATION

Inventor： Charles AUGUSTINE ,  Shigeki TOMISHIMA ,  James W. TSCHANZ ,  Shih-Lien L. LU

IPC: G11C11/16

CPC classification number: G11C11/1659 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

Abstract: In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.

Abstract translation: 根据本公开的各种实施例，描述了诸如自旋传递转矩（STT）随机存取存储器（RAM），STTRAM的MRAM存储器中的杂散磁场减轻。 在一个实施例中，可以通过产生磁场来补偿可能导致存储器的位单元改变状态的杂散磁场来促进STTRAM中位单元位值存储状态的保持。 在另一个实施例中，可以通过选择性地暂停对一行存储器的访问来临时终止可能导致存储器的位单元改变状态的杂散磁场来促进STTRAM中位单元位值存储状态的保持。 本文描述了其它方面。

公开(公告)号：US20160232968A1

公开(公告)日：2016-08-11

申请号：US15025229

申请日：2013-12-05

Applicant: INTEL CORPORATION

Inventor： Nathaniel J. AUGUST ,  Pulkit JAIN ,  Stefan RUSU ,  Fatih HAMZAOGLU ,  Rangharajan VENKATESAN ,  Muhammad KHELLAH ,  Charles AUGUSTINE ,  Carlos TOKUNAGA ,  James W. TSCHANZ ,  Yih WANG

IPC: G11C13/00 ,  G11C14/00 ,  G11C11/16

CPC classification number: G11C13/0061 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0011 ,  G11C13/0014 ,  G11C14/0081 ,  G11C14/009

Abstract: Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.

Abstract translation: 描述了一种包括使用电阻性存储器保持的存储单元的装置。 该装置包括：存储元件，包括交叉耦合到第二反相器件的第一反相器件; 具有至少一个电阻性存储器元件的恢复电路，所述恢复电路耦合到所述第一反相器件的输出; 耦合到所述第一反相装置的输出的第三反相装置; 耦合到第三反相装置的输出的第四反相装置; 以及具有至少一个电阻性存储器元件的保存电路，所述保存电路耦合到所述第三反相器件的输出端。