公开(公告)号：US20170178710A1

公开(公告)日：2017-06-22

申请号：US15115461

申请日：2014-03-07

Applicant: Intel Corporation

Inventor： Charles AUGUSTINE ,  Carlos TOKUNAGA ,  James W. TSCHANZ

IPC: G11C11/16 ,  H03M1/12

CPC classification number: G11C11/1695 ,  G06F21/34 ,  G06F21/73 ,  G06F21/79 ,  G09C1/00 ,  G11C7/16 ,  G11C7/24 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0059 ,  G11C2013/0045 ,  G11C2013/005 ,  H03M1/12 ,  H03M1/124 ,  H04L9/0866

Abstract: Described is a physically unclonable functional circuit comprising: a resistive memory device (e.g., an MTJ device) having at least two terminals; a transistor coupled to one of the at least two terminals of the resistive memory device; and an analog-to-digital converter (ADC) having an input coupled to the one of the at least two terminals of the resistive memory device.

公开(公告)号：US20220107867A1

公开(公告)日：2022-04-07

申请号：US17553623

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Wei WU ,  Carlos TOKUNAGA ,  Gregory K. CHEN

IPC: G06F11/10

Abstract: A near memory compute system includes multiple computation nodes, such as nodes for parallel distributed processing. The nodes include a memory device to store data and compute hardware to perform a computation on the data. Error correction code (ECC) logic performs ECC on the data prior to computation on the data by the compute hardware. The node also includes residue check logic to perform a residue check on a result of the computation.

公开(公告)号：US20180166145A1

公开(公告)日：2018-06-14

申请号：US15373048

申请日：2016-12-08

Applicant: Intel Corporation

Inventor： Minki CHO ,  Jaydeep KULKARNI ,  Carlos TOKUNAGA ,  Muhammad KHELLAH ,  James TSCHANZ

IPC: G11C29/12 ,  G11C5/14 ,  G11C11/417

CPC classification number: G11C11/417 ,  G11C5/14 ,  G11C11/4125 ,  G11C11/413 ,  G11C29/12005 ,  G11C29/24 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/50016 ,  G11C29/52 ,  G11C2029/0401 ,  G11C2029/1206 ,  G11C2029/5004

Abstract: An apparatus is described. The apparatus includes a semiconductor chip. The semiconductor chip includes a memory having multiple storage cells. The storage cells are to receive a supply voltage. The semiconductor chip includes supply voltage retention circuitry. The supply voltage retention circuitry is to determine a level of the supply voltage at which the storage cells are able to retain their respective data. The supply voltage retention circuitry is to receive the supply voltage during a stress mode of the supply voltage retention circuitry. The supply voltage retention circuitry is to more weakly retain its stored information than the storage cells during a measurement mode at which the level is determined.

公开(公告)号：US20160232968A1

公开(公告)日：2016-08-11

申请号：US15025229

申请日：2013-12-05

Applicant: INTEL CORPORATION

Inventor： Nathaniel J. AUGUST ,  Pulkit JAIN ,  Stefan RUSU ,  Fatih HAMZAOGLU ,  Rangharajan VENKATESAN ,  Muhammad KHELLAH ,  Charles AUGUSTINE ,  Carlos TOKUNAGA ,  James W. TSCHANZ ,  Yih WANG

IPC: G11C13/00 ,  G11C14/00 ,  G11C11/16

CPC classification number: G11C13/0061 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0011 ,  G11C13/0014 ,  G11C14/0081 ,  G11C14/009

Abstract: Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.

Abstract translation: 描述了一种包括使用电阻性存储器保持的存储单元的装置。 该装置包括：存储元件，包括交叉耦合到第二反相器件的第一反相器件; 具有至少一个电阻性存储器元件的恢复电路，所述恢复电路耦合到所述第一反相器件的输出; 耦合到所述第一反相装置的输出的第三反相装置; 耦合到第三反相装置的输出的第四反相装置; 以及具有至少一个电阻性存储器元件的保存电路，所述保存电路耦合到所述第三反相器件的输出端。