公开(公告)号：US20170011793A1

公开(公告)日：2017-01-12

申请号：US15115464

申请日：2014-03-05

Applicant: INTEL CORPORATION

Inventor： Gururaj K. SHAMANNA ,  Stefan RUSU ,  Eric A. KARL ,  Zheng GUO

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/04 ,  G11C7/22 ,  G11C29/021 ,  G11C29/028

Abstract: Described is an apparatus which comprises: a memory; a first power supply node to receive a first power supply; a second power supply node coupled to the memory to provide the memory with second power supply; a circuit coupled to the first and second power supply nodes, the circuit operable to dynamically modulate droop in the second power supply by adaptively adjusting signal characteristics of a write assist pulse.

Abstract translation: 描述了一种装置，包括：存储器; 第一电源节点，用于接收第一电源; 耦合到所述存储器以向所述存储器提供第二电源的第二电源节点; 耦合到所述第一和第二电源节点的电路，所述电路可操作以通过自适应地调整写入辅助脉冲的信号特性来动态地调制所述第二电源中的下降。

公开(公告)号：US20190157152A1

公开(公告)日：2019-05-23

申请号：US16252420

申请日：2019-01-18

Applicant: Intel Corporation

Inventor： Sujit SHARAN ,  Ravindranath MAHAJAN ,  Stefan RUSU ,  Donald S. GARDNER

IPC: H01L21/78 ,  H01L25/16 ,  H01L49/02 ,  H01L23/48 ,  H01L23/522

Abstract: Integrated passive components in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the substrate over the substrate, the first die including a power supply circuit coupled to the substrate to receive power, a second die having a processing core and coupled to the first die over the first die, the first die being coupled to the power supply circuit to power the processing core, a via through the first die, and a passive device formed in the via of the first die and coupled to the power supply circuit.

公开(公告)号：US20190081630A1

公开(公告)日：2019-03-14

申请号：US16184794

申请日：2018-11-08

Applicant: Intel Corporation

Inventor： Shenggao LI ,  Stefan RUSU

IPC: H03L7/00 ,  G06F13/40 ,  H03L7/091 ,  H01L25/065 ,  G06F1/12 ,  H03L7/081 ,  H03L7/07 ,  H04L7/00 ,  H01L23/48

CPC classification number: H03L7/00 ,  G06F1/12 ,  G06F13/4027 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2225/06541 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0012 ,  H04L7/0025 ,  Y02D10/14 ,  Y02D10/151

Abstract: Described is an apparatus for clock synchronization. The apparatus comprises a pair of interconnects; a first die including a first phase interpolator having an output coupled to one of the interconnects; and a second die, wherein the pair of interconnects is to couple the first die to the second die.

公开(公告)号：US20160232968A1

公开(公告)日：2016-08-11

申请号：US15025229

申请日：2013-12-05

Applicant: INTEL CORPORATION

Inventor： Nathaniel J. AUGUST ,  Pulkit JAIN ,  Stefan RUSU ,  Fatih HAMZAOGLU ,  Rangharajan VENKATESAN ,  Muhammad KHELLAH ,  Charles AUGUSTINE ,  Carlos TOKUNAGA ,  James W. TSCHANZ ,  Yih WANG

IPC: G11C13/00 ,  G11C14/00 ,  G11C11/16

CPC classification number: G11C13/0061 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0011 ,  G11C13/0014 ,  G11C14/0081 ,  G11C14/009

Abstract: Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.

Abstract translation: 描述了一种包括使用电阻性存储器保持的存储单元的装置。 该装置包括：存储元件，包括交叉耦合到第二反相器件的第一反相器件; 具有至少一个电阻性存储器元件的恢复电路，所述恢复电路耦合到所述第一反相器件的输出; 耦合到所述第一反相装置的输出的第三反相装置; 耦合到第三反相装置的输出的第四反相装置; 以及具有至少一个电阻性存储器元件的保存电路，所述保存电路耦合到所述第三反相器件的输出端。