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    Transistors with temperature compensating gate structures
    11.
    发明授权
    Transistors with temperature compensating gate structures 有权

    公开(公告)号：US10553694B2

    公开(公告)日：2020-02-04

    申请号：US16474874

    申请日：2017-04-11

    Applicant: INTEL CORPORATION

    Inventor： Uygar E. Avci ,  Daniel H. Morris ,  Ian A. Young

    IPC: H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66

    Abstract: Techniques are disclosed for forming semiconductor integrated circuits including a channel region, a gate dielectric between the gate electrode and the channel region, a first layer between the gate dielectric and the gate electrode, the first layer comprising temperature compensation material. In addition, the integrate circuit includes a source region adjacent to the channel region, a source metal contact on the source region, a drain region adjacent to the channel region, and a drain metal contact on the drain region. The temperature compensation material has a temperature dependent band structure, work-function, or polarization that dynamically adjusts the threshold voltage of the transistor in response to increased operating temperature to maintain the off-state current Ioff stable or otherwise within an acceptable tolerance. The temperature compensation material may be used in conjunction with a work function material to help provide desired performance at lower or non-elevated temperatures.

    One transistor and one ferroelectric capacitor memory cells in diagonal arrangements
    14.
    发明授权
    One transistor and one ferroelectric capacitor memory cells in diagonal arrangements 有权

    公开(公告)号：US11450675B2

    公开(公告)日：2022-09-20

    申请号：US16132281

    申请日：2018-09-14

    Applicant: Intel Corporation

    Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

    IPC: G11C11/22 ,  H01L27/11507 ,  H01L27/108 ,  H01L23/522 ,  H01L23/532

    Abstract: Described herein are one access transistor and one ferroelectric capacitor (1T-1FE-CAP) memory cells in diagonal arrangements, as well as corresponding methods and devices. When access transistors of memory cells are implemented as FinFETs, then, in a first diagonal arrangement, memory cells are arranged so that the BLs for the cells are diagonal with respect to the fins of the access transistors of the cells, while the WLs for the cells are perpendicular to the fins. In a second diagonal arrangement, memory cells are arranged so that the fins of the access transistors of the cells are diagonal with respect to the WLs for the cells, while the BLs for the cells are perpendicular to the WLs. Such diagonal arrangements may advantageously allow achieving high layout densities of 1T-1FE-CAP memory cells and may benefit from the re-use of front-end transistor process technology with relatively minor adaptations.

    ANTI-FERROELECTRIC CAPACITOR MEMORY CELL
    15.
    发明申请
    ANTI-FERROELECTRIC CAPACITOR MEMORY CELL 有权

    公开(公告)号：US20220231035A1

    公开(公告)日：2022-07-21

    申请号：US17713790

    申请日：2022-04-05

    Applicant: Intel Corporation

    Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

    IPC: H01L27/11507 ,  G11C11/22 ,  H01L49/02

    Abstract: Described herein are anti-ferroelectric (AFE) memory cells and corresponding methods and devices. For example, in some embodiments, an AFE memory cell disclosed herein includes a capacitor employing an AFE material between two capacitor electrodes. Applying a voltage to one electrode of such capacitor allows boosting the charge at the other electrode, where nonlinear behavior of the AFE material between the two electrodes may advantageously manifest itself in that, for a given voltage applied to the first electrode, a factor by which the charge is boosted at the second electrode of the capacitor may be substantially different for different values of charge at that electrode before the boost. Connecting the second capacitor electrode to a storage node of the memory cell may then allow boosting the charge on the storage node so that different logic states of the memory cell become more clearly resolvable, enabling increased retention times.

    Polarization gate stack SRAM
    17.
    发明授权
    Polarization gate stack SRAM 有权

    公开(公告)号：US11232832B2

    公开(公告)日：2022-01-25

    申请号：US17061272

    申请日：2020-10-01

    Applicant: Intel Corporation

    Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

    IPC: G11C11/00 ,  G11C11/412 ,  G11C8/16 ,  G11C11/419 ,  H01L27/11 ,  G11C11/22

    Abstract: One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.

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