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    APPARATUS AND METHOD FOR DRIFT CANCELLATION IN A MEMORY
    11.
    发明申请
    APPARATUS AND METHOD FOR DRIFT CANCELLATION IN A MEMORY 有权
    在存储器中删除取消的装置和方法

    公开(公告)号：US20160284399A1

    公开(公告)日：2016-09-29

    申请号：US14671972

    申请日：2015-03-27

    Applicant: Intel Corporation

    Inventor： Davide Mantegazza ,  Prashant S. Damle ,  Kiran Pangal ,  Hanmant P. Belgal ,  Abhinav Pandey

    IPC: G11C13/00 ,  G11C11/56

    CPC classification number: G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0052 ,  G11C2013/0057 ,  G11C2013/0083

    Abstract: An apparatus is provided which comprises: a plurality of memory cells; a bias logic coupled with at least one memory cell of the plurality, the bias logic to: apply a first read voltage to the at least one memory cell; and apply a second read voltage to the at least one memory cell, the first read voltage being higher than the second read voltage; and a first circuit operable to float a word-line coupled to the at least one memory cell before the bias logic applies the first read voltage to the at least one memory cell. A method is provided which comprises: performing a first read operation to at least one memory cell; and performing a second read operation to the at least one memory cell after the first read operation completes, wherein the second read operation is different from the first read operation.

    Abstract translation: 提供了一种装置，包括：多个存储单元; 偏置逻辑与所述多个存储单元中的至少一个存储单元耦合，所述偏置逻辑用于：将第一读取电压施加到所述至少一个存储单元; 并且向所述至少一个存储单元施加第二读取电压，所述第一读取电压高于所述第二读取电压; 以及第一电路，其可操作以在所述偏置逻辑将所述第一读取电压施加到所述至少一个存储器单元之前，浮动耦合到所述至少一个存储器单元的字线。 提供了一种方法，其包括：对至少一个存储单元执行第一读取操作; 以及在所述第一读取操作完成之后对所述至少一个存储器单元执行第二读取操作，其中所述第二读取操作与所述第一读取操作不同。

    Set and reset operation in phase change memory and associated techniques and configurations
    13.
    发明授权
    Set and reset operation in phase change memory and associated techniques and configurations 有权
    在相变存储器和相关技术和配置中设置和复位操作

    公开(公告)号：US09368205B2

    公开(公告)日：2016-06-14

    申请号：US14010417

    申请日：2013-08-26

    Applicant: INTEL CORPORATION

    Inventor： Davide Mantegazza ,  Kiran Pangal ,  Gerard H. Joyce ,  Prashant Damle ,  Derchang Kau ,  Davide Fugazza

    IPC: G11C13/00

    CPC classification number: G11C13/0097 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0092

    Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In an embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device, wherein the memory cell is coupled with a capacitor and subsequent to said increasing the current, generating a transient current through the memory cell by discharge of the capacitor to reset the memory cell. In another embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device and controlling the current to be greater than a threshold current and lower than a hold current of the memory cell to set the memory cell. Other embodiments may be described and/or claimed.

    Abstract translation: 本公开的实施例描述了在相变存储器（PCM）设备中的字线路径隔离的技术和配置。 在一个实施例中，一种方法包括增加通过相变存储器（PCM）器件的存储器单元的电流，其中存储器单元与电容器耦合，并且随后增加电流，产生通过存储器单元的瞬态电流，由 放电电容器来重置存储单元。 在另一个实施例中，一种方法包括增加通过相变存储器（PCM）器件的存储器单元的电流，并且控制电流大于阈值电流并且低于存储器单元的保持电流以设置存储器单元。 可以描述和/或要求保护其他实施例。

    Techniques to mitigate error during a read operation to a memory array
    14.
    发明授权
    Techniques to mitigate error during a read operation to a memory array 有权

    公开(公告)号：US11145366B1

    公开(公告)日：2021-10-12

    申请号：US16828860

    申请日：2020-03-24

    Applicant: Intel Corporation

    Inventor： Davide Mantegazza ,  Kiran Pangal

    IPC: G11C11/00 ,  G11C13/00 ,  G11C29/12 ,  G11C29/50 ,  G11C29/44

    Abstract: Examples may include techniques to mitigate errors during a read operation to a memory cell of a memory array. Examples include selecting the memory cell and applying one of multiple demarcation read voltages for respective multiple time intervals to sense a state of a resistive storage element of the memory cell. Examples also include applying a bias voltage to the memory cell following a sense interval to mitigate read disturb to the resistive storage element incurred while the one of the multiple demarcation read voltages was applied to the memory cell.

    Selection scheme for crosspoint memory
    15.
    发明授权
    Selection scheme for crosspoint memory 有权

    公开(公告)号：US11100987B1

    公开(公告)日：2021-08-24

    申请号：US16831639

    申请日：2020-03-26

    Applicant: Intel Corporation

    Inventor： Davide Mantegazza ,  Kyung Jean Yoon ,  John Gorman ,  Dany-Sebastien Ly-Gagnon

    IPC: G11C13/00 ,  G11C11/56

    Abstract: A selection scheme for crosspoint memory is described. In one example, the selection voltage applied across the memory cell is slowly ramped up. Once the memory cell thresholds, the voltage is reduced to a level for performing the read or write operation. Reducing the voltage once the specific cell has been selected (e.g., thresholds) minimizes the additional transient current which might be generated by further increasing the selection bias applied during read or write operation. The reduction in transient current can lead to an improvement in read disturb and write endurance issues. The selection ramp-rate and bias post-selection can be set differently depending on the cell location inside the memory array to further improve cell performance.

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