公开(公告)号：US20220012016A1

公开(公告)日：2022-01-13

申请号：US17485179

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Renzhi Liu ,  Richard Dorrance ,  Deepak Dasalukunte

IPC: G06F7/544 ,  G06F7/523 ,  G06N3/04 ,  H03M1/78 ,  H03M1/80

Abstract: Systems, apparatuses and methods include technology that receives, with a first plurality of multipliers of a multiply-accumulator (MAC), first digital signals from a memory array, wherein the first plurality of multipliers includes a plurality of capacitors. The technology further executes, with the first plurality of multipliers, multibit computation operations with the plurality of capacitors based on the first digital signals, and generates, with the first plurality of multipliers, a first analog signal based on the multibit computation operations.

公开(公告)号：US12254399B2

公开(公告)日：2025-03-18

申请号：US17159312

申请日：2021-01-27

Applicant: Intel Corporation

Inventor： Deepak Dasalukunte ,  Richard Dorrance ,  Hechen Wang

IPC: G06N3/065 ,  G06N3/047 ,  H04L45/586 ,  H04L49/109

Abstract: Systems, methods, apparatuses, and computer-readable media. An analog router of a first supertile of a plurality of supertiles of a network on a chip (NoC) may receive a first analog output from a first compute-in-memory tile of a plurality of compute-in-memory tiles of the first supertile. The analog router may determine, based on a configuration of a neural network executing on the NoC, that a destination of the first analog output includes a second supertile of the plurality of supertiles. An analog-to-digital converter (ADC) of the analog router may convert the first analog output to a first digital output and transmit the first digital output to the second supertile via a communications bus of the NoC.

公开(公告)号：US12131245B2

公开(公告)日：2024-10-29

申请号：US17075527

申请日：2020-10-20

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Richard Dorrance ,  Deepak Dasalukunte ,  David Israel Gonzalez Aguirre

IPC: G06N3/04 ,  G06F1/06 ,  H03L7/089 ,  H03L7/099 ,  G11C11/412

CPC classification number: G06N3/04 ,  G06F1/06 ,  H03L7/0891 ,  H03L7/0995 ,  G11C11/412

Abstract: Methods, apparatus, systems, and articles of manufacture providing an improved Bayesian neural network and methods and apparatus to operate the same are disclosed. An example apparatus includes an oscillator to generate a first clock signal; a resistive element to adjust a slope of a rising edge of a second clock signal; a voltage sampler to generate a sample based on at least one of (a) a first voltage of the first clock signal when a second voltage of the second clock signal satisfies a threshold or (b) a third voltage of the second clock signal when a fourth voltage of the first clock signal satisfies the threshold; and a charge pump to adjust a weight based on the sample, the weight to adjust data in a model.

公开(公告)号：US20240045723A1

公开(公告)日：2024-02-08

申请号：US18477816

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Deepak Dasalukunte ,  Richard Dorrance ,  Renzhi Liu ,  Henchen Wang ,  Brent Carlton

IPC: G06F9/50 ,  G11C7/10

CPC classification number: G06F9/5033 ,  G06F9/5016 ,  G11C7/1012

Abstract: Systems, apparatuses and methods include technology that executes, with a compute-in-memory (CiM) element, first computations based on first data associated with a workload, and a storage of the first data, executes, with a compute-near memory (CnM) element, second computations based on second data associated with the workload and executes, with a compute-outside-of-memory (CoM) element, third computations based on third data associated with the workload. The technology further receives, with a multiplexer, processed data from a first element of the CiM element, the CnM element and the CoM element, and provides, with the multiplexer, the processed data to a second element of the CiM element, the CnM element and the CoM element.

公开(公告)号：US20230289066A1

公开(公告)日：2023-09-14

申请号：US18187950

申请日：2023-03-22

Applicant: Intel Corporation

Inventor： Renzhi Liu ,  Hechen Wang ,  Richard Dorrance ,  Deepak Dasalukunte ,  Brent Carlton

IPC: G06F3/06 ,  G06N3/0464 ,  G06F7/544

CPC classification number: G06F3/0613 ,  G06N3/0464 ,  G06F3/0659 ,  G06F3/0673 ,  G06F7/5443

Abstract: Systems, apparatuses and methods may provide for technology that includes a memory array to store multibit weight data and a capacitor ladder network to conduct multiply-accumulate (MAC) operations on first analog signals and multibit weight data, the capacitor ladder network further to output second analog signals based on the MAC operations, wherein the capacitor ladder network is external to the memory array. In one example, the capacitor ladder network includes a plurality of switches and the logic includes a controller to selectively activate the plurality of switches based on a data format of the multibit weight data.

公开(公告)号：US20230229504A1

公开(公告)日：2023-07-20

申请号：US17937248

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Renzhi Liu ,  Hechen Wang ,  Richard Dorrance ,  Deepak Dasalukunte ,  Brent Carlton

IPC: G06F9/50 ,  G06F7/544 ,  H03M1/18

CPC classification number: G06F9/5027 ,  G06F7/5443 ,  H03M1/18

Abstract: Systems, apparatuses and methods may provide for compute-in-memory (CiM) accelerator technology that includes a multiply-accumulate (MAC) computation stage, an analog amplifier stage coupled to an output of the MAC computation stage, and an analog to digital conversion (ADC) stage coupled to an output of the analog amplifier stage, wherein a gain setting of the analog amplifier stage modifies a quantization granularity of the ADC stage.

公开(公告)号：US20220209891A1

公开(公告)日：2022-06-30

申请号：US17134255

申请日：2020-12-25

Applicant: Intel Corporation

Inventor： Sundar Krishnamurthy ,  Lu Lu ,  Niranjan Mylarapa Gowda ,  Le Liang ,  Richard Dorrance ,  Deepak Dasalukunte ,  Arvind Merwaday

IPC: H04L1/00 ,  H04L27/38 ,  H04L25/02

Abstract: Bayesian Inference based communication receiver employs Markov-Chain Monte-Carlo (MCMC) sampling for performing several of the main receiver functionalities. The channel estimator estimates the multipath channel coefficients corresponding to a signal received with fading. The symbol demodulator demodulates the received signal according to a QAM constellation, so as to generate a demodulated signal, and estimate the transmitted symbols. The decoder reliably decodes the demodulated signals to generate an output bit sequence, factoring in redundancy induced at a certain code rate. A universal sampler may be configured to use MCMC sampling for generating estimates of channel coefficients, transmitted symbols or decoder bits, for aforementioned functionalities, respectively. The samples may then be used in one or more of the receiver tasks: channel estimation, signal demodulation, and decoding, which leads to a more scalable, reusable, power/area efficient receiver.

公开(公告)号：US12141547B2

公开(公告)日：2024-11-12

申请号：US17131482

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Deepak Dasalukunte ,  Richard Dorrance ,  David Gonzales Aguirre

IPC: G06F7/58

Abstract: Techniques and mechanisms providing a mode of random number generation to satisfy a requirement for a consumer of random numbers. In an embodiment, a device comprises a Gaussian random number generator (GRNG) circuit, multiple uniform random number generator URNG circuits, and circuitry which is coupled between the GRNG circuit and the URNG circuits. Based on an indication of one or more required performance characteristics and/or one or more required statistical characteristics, a controller identifies a corresponding one of multiple available random number generation (RNG) modes. The controller communicates control signals to provide the mode with the circuitry. In another embodiment, the control signals configure the circuitry to select one or more of the URNG circuits for use in calculating random numbers with the GRNG circuit.

公开(公告)号：US12126440B2

公开(公告)日：2024-10-22

申请号：US17134255

申请日：2020-12-25

Applicant: Intel Corporation

Inventor： Sundar Krishnamurthy ,  Lu Lu ,  Niranjan Mylarappa Gowda ,  Le Liang ,  Richard Dorrance ,  Deepak Dasalukunte ,  Arvind Merwaday

IPC: H04L27/06 ,  H04L1/00 ,  H04L25/02 ,  H04L27/38

CPC classification number: H04L1/0053 ,  H04L1/0054 ,  H04L25/0256 ,  H04L27/38

Abstract: Bayesian Inference based communication receiver employs Markov-Chain Monte-Carlo (MCMC) sampling for performing several of the main receiver functionalities. The channel estimator estimates the multipath channel coefficients corresponding to a signal received with fading. The symbol demodulator demodulates the received signal according to a QAM constellation, so as to generate a demodulated signal, and estimate the transmitted symbols. The decoder reliably decodes the demodulated signals to generate an output bit sequence, factoring in redundancy induced at a certain code rate. A universal sampler may be configured to use MCMC sampling for generating estimates of channel coefficients, transmitted symbols or decoder bits, for aforementioned functionalities, respectively. The samples may then be used in one or more of the receiver tasks: channel estimation, signal demodulation, and decoding, which leads to a more scalable, reusable, power/area efficient receiver.

公开(公告)号：US20240235665A9

公开(公告)日：2024-07-11

申请号：US17972965

申请日：2022-10-25

Applicant: Intel Corporation

Inventor： Sundar Krishnamurthy ,  Conor O'Keeffe ,  Deepak Dasalukunte ,  Finbarr O'Regan ,  Abhinav Vinod

IPC: H04B7/185

CPC classification number: H04B7/1855 ,  H04B7/18513 ,  H04B7/18521 ,  H04B7/18543

Abstract: An apparatus can include transceiver circuitry to receive an input signal from a target apparatus. The apparatus can further include a processing circuitry to determine position information of a source object and a target object. Based on the position information, the processing circuitry can calculate a relative velocity and determine a Doppler shift or carrier frequency offset in the input signal based on the relative velocity. The processing circuitry can adjust a local oscillator frequency based on a Doppler measured using the position information in an initial link acquisition phase. The processing circuitry can track the Doppler continuously over a range of tens of gigahertz accounting for Doppler phase ambiguities, and correct for a tracked Doppler shift by partially adjusting a local oscillator frequency and by correcting a residual Doppler shift digitally.