公开(公告)号：US20210182068A1

公开(公告)日：2021-06-17

申请号：US16714667

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： MOHAMED ELMALAKI ,  ELMOUSTAPHA OULD-AHMED-VALL

IPC: G06F9/30

Abstract: Systems, methods, and apparatuses relating to instructions to multiply floating-point values of about zero are described. In one embodiment, a hardware processor includes a decoder to decode a single instruction into a decoded single instruction, the single instruction having a first field that identifies a first floating-point number, a second field that identifies a second floating-point number, and a third field that indicates an about zero threshold; and an execution circuit to execute the decoded single instruction to: cause a first comparison of an exponent of the first floating-point number to the about zero threshold, cause a second comparison of an exponent of the second floating-point number to the about zero threshold, provide as a resultant of the single instruction a value of zero when the first comparison indicates the exponent of the first floating-point number does not exceed the about zero threshold, provide as the resultant of the single instruction the value of zero when the second comparison indicates the exponent of the second floating-point number does not exceed the about zero threshold, and provide as the resultant of the single instruction a product of a multiplication of the first floating-point number and the second floating-point number when the first comparison indicates the exponent of the first floating-point number exceeds the about zero threshold and the second comparison indicates the exponent of the second floating-point number exceeds the about zero threshold.

公开(公告)号：US20180307494A1

公开(公告)日：2018-10-25

申请号：US15494773

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  BARATH LAKSHMANAN ,  TATIANA SHPEISMAN ,  Joydeep Ray ,  Ping T. Tang ,  Michael Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Ben J. Ashbaugh ,  Linda L. Hurd ,  Liwei Ma

IPC: G06F9/38 ,  G06F9/30 ,  G06F13/42 ,  G06F13/40 ,  G06N99/00

CPC classification number: G06F9/3887 ,  G06F1/32 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3016 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/50 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/80 ,  G06F2213/0026 ,  G06N3/00 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/084 ,  G06N20/00 ,  G06T1/20

Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising instruction decode logic to decode a single instruction including multiple operands into a single decoded instruction, the multiple operands having differing precisions and a general-purpose graphics compute unit including a first logic unit and a second logic unit, the general-purpose graphics compute unit to execute the single decoded instruction, wherein to execute the single decoded instruction includes to perform a first instruction operation on a first set of operands of the multiple operands at a first precision and a simultaneously perform second instruction operation on a second set of operands of the multiple operands at a second precision.

公开(公告)号：US20180300964A1

公开(公告)日：2018-10-18

申请号：US15488914

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： BARATH LAKSHAMANAN ,  LINDA L. HURD ,  BEN J. ASHBAUGH ,  ELMOUSTAPHA OULD-AHMED-VALL ,  LIWEI MA ,  JINGYI JIN ,  JUSTIN E. GOTTSCHLICH ,  CHANDRASEKARAN SAKTHIVEL ,  MICHAEL S. STRICKLAND ,  BRIAN T. LEWIS ,  LINDSEY KUPER ,  ALTUG KOKER ,  ABHISHEK R. APPU ,  PRASOONKUMAR SURTI ,  JOYDEEP RAY ,  BALAJI VEMBU ,  JAVIER S. TUREK ,  NAILA FAROOQUI

IPC: G07C5/00 ,  G05D1/00 ,  G01C21/34 ,  G08G1/052 ,  G08G1/01 ,  H04W28/08 ,  G06N99/00

CPC classification number: G07C5/008 ,  B60W30/00 ,  G01C21/34 ,  G01S19/13 ,  G05D1/0088 ,  G05D2201/0213 ,  G06F9/5027 ,  G06F2209/509 ,  G06N20/00 ,  G08G1/0112 ,  G08G1/012 ,  G08G1/052 ,  H04L43/0852 ,  H04L67/12 ,  H04W28/08

Abstract: One embodiment provides for a computing device within an autonomous vehicle, the compute device comprising a wireless network device to enable a wireless data connection with an autonomous vehicle network, a set of multiple processors including a general-purpose processor and a general-purpose graphics processor, the set of multiple processors to execute a compute manager to manage execution of compute workloads associated with the autonomous vehicle, the compute workload associated with autonomous operations of the autonomous vehicle, and offload logic configured to execute on the set of multiple processors, the offload logic to determine to offload one or more of the compute workloads to one or more autonomous vehicles within range of the wireless network device.

公开(公告)号：US20180081689A1

公开(公告)日：2018-03-22

申请号：US15809818

申请日：2017-11-10

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE ,  JESUS CORBAL ,  BRET L. TOLL ,  MARK J. CHARNEY ,  ZEEV SPERBER ,  AMIT GRADSTEIN

IPC: G06F9/30

Abstract: An apparatus is described that includes instruction execution circuitry to execute first, second, third, and fourth instructions, the first and second instructions select a first group of input vector elements from one of multiple first non-overlapping sections of respective first and second input vectors. Each of the multiple first non-overlapping sections have a same bit width as the first group. Both the third and fourth instructions select a second group of input vector elements from one of multiple second non-overlapping sections of respective third and fourth input vectors. The second group has a second bit width that is larger than the first bit width. Each of multiple second non-overlapping sections have a same bit width as the second group. The apparatus includes masking layer circuitry to mask the first and second groups at a first granularity and second granularity.

公开(公告)号：US20170206087A1

公开(公告)日：2017-07-20

申请号：US15478520

申请日：2017-04-04

Applicant: Intel Corporation

Inventor： MIKHAIL PLOTNIKOV ,  ANDREY NARAIKIN ,  ELMOUSTAPHA OULD-AHMED-VALL

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/3016 ,  G06F9/325

Abstract: In an embodiment, the present invention is directed to a processor including a decode logic to receive a multi-dimensional loop counter update instruction and to decode the multi-dimensional loop counter update instruction into at least one decoded instruction, and an execution logic to execute the at least one decoded instruction to update at least one loop counter value of a first operand associated with the multi-dimensional loop counter update instruction by a first amount. Methods to collapse loops using such instructions are also disclosed. Other embodiments are described and claimed.

公开(公告)号：US20170075691A1

公开(公告)日：2017-03-16

申请号：US15363785

申请日：2016-11-29

Applicant: Intel Corporation

Inventor： MIKHAIL PLOTNIKOV ,  ANDREY NARAIKIN ,  ELMOUSTAPHA OULD-AHMED-VALL

IPC: G06F9/355 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3555 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/355 ,  G06F9/3802 ,  G06F9/3893

Abstract: An apparatus is described having functional unit logic circuitry. The functional unit logic circuitry has a first register to store a first input vector operand having an element for each dimension of a multi-dimensional data structure. Each element of the first vector operand specifying the size of its respective dimension. The functional unit has a second register to store a second input vector operand specifying coordinates of a particular segment of the multi-dimensional structure. The functional unit also has logic circuitry to calculate an address offset for the particular segment relative to an address of an origin segment of the multi-dimensional structure.

Abstract translation: 描述了具有功能单元逻辑电路的装置。 功能单元逻辑电路具有第一寄存器以存储具有用于多维数据结构的每个维度的元素的第一输入向量操作数。 第一个向量操作数的每个元素指定其相应维度的大小。 功能单元具有第二寄存器，用于存储指定多维结构的特定段的坐标的第二输入向量操作数。 功能单元还具有逻辑电路，用于相对于多维结构的原点片段的地址计算特定片段的地址偏移。

公开(公告)号：US20160179529A1

公开(公告)日：2016-06-23

申请号：US14581738

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： JESUS CORBAL ,  ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE ,  MARK J. CHARNEY

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30032

Abstract: An apparatus and method for performing a vector bit reversal and crossing. For example, one embodiment of a processor comprises: a first source vector register to store a first plurality of source bit groups, wherein a size for the bit groups is to be specified in an immediate of an instruction; a second source vector to store a second plurality of source bit groups; vector bit reversal and crossing logic to determine a bit group size from the immediate and to responsively reverse positions of contiguous bit groups within the first source vector register to generate a set of reversed bit groups, wherein the vector bit reversal and crossing logic is to additionally interleave the set of reversed bit groups with the second plurality of bit groups; and a destination vector register to store the reversed bit groups interleaved with the first plurality of bit groups.

Abstract translation: 用于执行向量位反转和交叉的装置和方法。 例如，处理器的一个实施例包括：第一源向量寄存器，用于存储第一多个源位组，其中用于位组的大小将在指令的立即指定中; 用于存储第二多个源比特组的第二源向量; 矢量位反转和交叉逻辑，以从第一源向量寄存器内的连续位组的立即和响应地反向位置确定位组大小，以产生一组反向位组，其中向量位反转和交叉逻辑额外地 将所述一组反转位组与所述第二多个位组进行交织; 以及目的地向量寄存器，用于存储与第一多个比特组交织的反向比特组。

公开(公告)号：US20160179526A1

公开(公告)日：2016-06-23

申请号：US14581289

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： ASHISH JHA ,  ROBERT VALENTINE ,  ELMOUSTAPHA OULD-AHMED-VALL

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30043 ,  G06F9/30101 ,  G06F15/8053

Abstract: An apparatus and method for performing vector index loads and stores. For example, one embodiment of a processor comprises: a vector index register to store a plurality of index values; a mask register to store a plurality of mask bits; a vector register to store a plurality of vector data elements loaded from memory; and vector index load logic to identify an index stored in the vector index register to be used for a load operation using an immediate value and to responsively combine the index with a base memory address to determine a memory address for the load operation, the vector index load logic to load vector data elements from the memory address to the vector register in accordance with the plurality of mask bits.

Abstract translation: 用于执行向量索引加载和存储的装置和方法。 例如，处理器的一个实施例包括：矢量索引寄存器，用于存储多个索引值; 掩模寄存器，用于存储多个掩码位; 向量寄存器，用于存储从存储器加载的多个向量数据元素; 以及矢量索引负载逻辑，以识别存储在矢量索引寄存器中的索引，以用于使用立即值的加载操作，并且响应地将索引与基本存储器地址组合以确定用于加载操作的存储器地址，向量索引 负载逻辑，以根据多个掩码位将矢量数据元素从存储器地址加载到向量寄存器。

公开(公告)号：US20160179521A1

公开(公告)日：2016-06-23

申请号：US14581578

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： ASHISH JHA ,  ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE

IPC: G06F9/30

CPC classification number: G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30072

Abstract: An apparatus and method for performing a mask expand. For example, one embodiment of a processor comprises: a source mask register to store a plurality of mask values; mask expand logic to identify a first mask bit in the source mask register to be expanded using an index value and to determine a number of bit positions within a destination mask register into which the first mask bit is to be expanded using a second value, the mask expand logic to responsively copy the first mask bit to each of the determined bit positions within the destination mask register.

Abstract translation: 一种用于执行掩模扩展的装置和方法。 例如，处理器的一个实施例包括：源掩码寄存器，用于存储多个掩码值; 掩码扩展逻辑，以使用索引值来识别要被扩展的源掩码寄存器中的第一掩码位，并且使用第二值确定目标掩码寄存器中要扩展第一掩码位的位位数， 掩码扩展逻辑以将第一掩码位响应地复制到目的掩码寄存器中的每个确定的位位置。

公开(公告)号：US20230315481A1

公开(公告)日：2023-10-05

申请号：US18312079

申请日：2023-05-04

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  BARATH LAKSHMANAN ,  TATIANA SHPEISMAN ,  Joydeep Ray ,  Ping T. Tang ,  Michael Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Ben J. Ashbaugh ,  Linda L. Hurd ,  Liwei Ma

IPC: G06F9/38 ,  G06F9/30 ,  G06F13/42 ,  G06F13/40 ,  G06N20/00 ,  G06T1/20 ,  G06N3/063 ,  G06N3/084 ,  G06N20/10 ,  G06N3/044 ,  G06N3/045 ,  G06F9/50 ,  G06F15/80 ,  G06N3/00

CPC classification number: G06F9/3887 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3016 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/50 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/80 ,  G06N3/00 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084 ,  G06N20/00 ,  G06N20/10 ,  G06T1/20 ,  G06F2213/0026

Abstract: Described herein is a general-purpose graphics processing unit including a multiprocessor having a single instruction, multiple thread, SIMT, architecture. The multiprocessor comprises multiple sets of compute units each having a first logic unit configured to perform floating-point operations and a second logic unit configured to perform integer operations, with a thread of the floating-point instruction being executed in parallel with a thread of the integer instruction.