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    FORWARDED SUPPLY VOLTAGE FOR DYNAMIC VOLTAGE AND FREQUENCY SCALING WITH STACKED CHIP PACKAGING ARCHITECTURE
    13.
    发明公开
    FORWARDED SUPPLY VOLTAGE FOR DYNAMIC VOLTAGE AND FREQUENCY SCALING WITH STACKED CHIP PACKAGING ARCHITECTURE 审中-公开

    公开(公告)号：US20230245999A1

    公开(公告)日：2023-08-03

    申请号：US17588392

    申请日：2022-01-31

    Applicant: Intel Corporation

    Inventor： Gerald S. Pasdast ,  Peipei Wang ,  Adel A. Elsherbini

    IPC: H01L25/065 ,  H01L23/538 ,  H04B3/02

    CPC classification number: H01L25/0652 ,  H01L23/5383 ,  H01L23/5386 ,  H04B3/02

    Abstract: Embodiments of the present disclosure provide a microelectronic assembly comprising: a first integrated circuit (IC) die in a first layer; an interposer in a second layer not coplanar with the first layer, the first layer coupled to the second layer by interconnects having a pitch of less than 10 micrometers between adjacent interconnects; and a first conductive pathway and a second conductive pathway in the interposer coupling the first IC die and a second IC die. The first IC die is configured to transmit at a first supply voltage through the first conductive pathway to a second IC die, the second IC die is configured to transmit to the first IC die through the second conductive pathway at a second supply voltage simultaneously with the first die transmitting at the first supply voltage, and the first supply voltage is different from the second supply voltage.

    MULTICHIP PACKAGE LINK
    19.
    发明申请
    MULTICHIP PACKAGE LINK 有权
    多媒体包链接

    公开(公告)号：US20160283429A1

    公开(公告)日：2016-09-29

    申请号：US14669975

    申请日：2015-03-26

    Applicant: Intel Corporation

    Inventor： Mahesh Wagh ,  Zuoguo Wu ,  Venkatraman Iyer ,  Gerald S. Pasdast ,  Mark S. Birrittella ,  Ishwar Agarwal ,  Lip Khoon Teh ,  Su Wei Lim ,  Anoop Kumar Upadhyay

    IPC: G06F13/40 ,  G06F13/36 ,  G01R31/317

    CPC classification number: G06F13/4022 ,  G06F13/36 ,  G06F13/4068

    Abstract: A system-on-a-chip, such as a logical PHY, may be divided into hard IP blocks with fixed routing, and soft IP blocks with flexible routing. Each hard IP block may provide a fixed number of lanes. Using p hard IP blocks, where each block provides n data lanes, h=n*p total hard IP data lanes are provided. Where the system design calls for k total data lanes, it is possible that k≠h, so that [k/n] hard IP blocks provide h=n*p available hard IP data lanes. In that case, h−k lanes may be disabled. In cases where lane reversals occur, such as between hard IP and soft IP, bowtie routing may be avoided by the use of a multiplexer-like programmable switch within the soft IP.

    Abstract translation: 诸如逻辑PHY的片上系统可以被划分为具有固定路由的硬IP块和具有灵活路由的软IP块。 每个硬IP块可以提供固定数量的车道。 使用p硬IP块，其中每个块提供n个数据通道，h = n * p提供总硬IP数据通道。 在系统设计要求k个总数据通道的情况下，k≠h可以使得[k / n]硬IP块提供h = n * p可用的硬IP数据通道。 在这种情况下，h-k通道可能被禁用。 在发生通道反转的情况下，例如在硬IP和软IP之间，可以通过使用软IP内的多路复用器可编程开关来避免路由路由。

    METHOD, APPARATUS, SYSTEM FOR CENTERING IN A HIGH PERFORMANCE INTERCONNECT
    20.
    发明申请
    METHOD, APPARATUS, SYSTEM FOR CENTERING IN A HIGH PERFORMANCE INTERCONNECT 有权
    方法，设备，高性能互连中心的系统

    公开(公告)号：US20160191034A1

    公开(公告)日：2016-06-30

    申请号：US14583139

    申请日：2014-12-25

    Applicant: Intel Corporation

    Inventor： Mahesh Wagh ,  Zuoguo Wu ,  Venkatraman Iyer ,  Gerald S. Pasdast ,  Todd A. Hinck ,  David M. Lee ,  Narasimha R. Lanka

    IPC: H03K5/26 ,  G01R31/04 ,  H03L9/00

    CPC classification number: H03K5/26 ,  G01R31/041 ,  G06F1/3296 ,  G06F13/4291 ,  H03K5/131 ,  H03L9/00

    Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.

    Abstract translation: 在一个示例中，公开了一种用于以高性能互连（HPI）为中心的系统和方法。 当互连从休眠状态上电时，可能需要“中心”时钟信号，以确保在正确的时间读取数据。 可以使用多相方法，其中第一相包括参考电压扫描以识别最佳参考电压。 第二阶段包括相位扫描以识别最佳相位。 第三扫描包括二维“眼”阶段，其中测试从前两次扫描得到的二维眼睛内的多个值。 在每种情况下，最佳值是导致多个通道中最小位错误的值。 在一个示例中，第二和第三阶段以软件执行，并且可以包括测试“受害者”通道，具有具有互补位模式的相邻“侵略者”通道。

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