公开(公告)号：US10324124B2

公开(公告)日：2019-06-18

申请号：US14741346

申请日：2015-06-16

Applicant: INTEL CORPORATION

Inventor： Linda K. Sun ,  Harry Muljono

IPC: G01N27/22 ,  G01R31/28 ,  H01L21/66

Abstract: A pad capacitance test circuit may be coupled to one or more pads of an electronic circuit, such as a processor. The pad capacitance test circuit may be located on a die including the electronic circuit. The pad capacitance test circuit may reset a pad voltage of one or more of the pads to zero, and then couple the pad to a supply voltage through a pullup resistor for a time period. The final pad voltage at or near the end of the period of time may be measured. The pad capacitance may be determined from the measured value of the final pad voltage and known values of the supply voltage, the time period, and resistance of the pullup resistor.

公开(公告)号：US09602160B2

公开(公告)日：2017-03-21

申请号：US14521961

申请日：2014-10-23

Applicant: Intel Corporation

Inventor： Harry Muljono ,  Changhong Lin

IPC: H04B3/32 ,  H04J1/12 ,  H04J3/10 ,  G06F13/40 ,  H04L25/14

CPC classification number: H04B3/32 ,  G06F13/40 ,  H04J1/12 ,  H04J3/10 ,  H04L25/08 ,  H04L25/14

Abstract: Described is an apparatus which comprises: a first buffer to receive a first signal from a first transmission media; a second buffer to receive a second signal from a second transmission media separate from the first transmission media; a first summing node coupled to the first buffer, the first summing node to receive output of the first buffer; and a first digital adjustment circuit which is operable to drive a first adjustment signal to the first summing node when a transition edge of the second signal is detected.

公开(公告)号：US09306555B2

公开(公告)日：2016-04-05

申请号：US14136356

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Harry Muljono ,  Kai Xiao

IPC: H03K3/00 ,  H03B1/00 ,  H03K17/0412 ,  H03K17/16 ,  H03K17/687 ,  H03K19/0185

CPC classification number: H03K17/04123 ,  H03K17/162 ,  H03K17/6871 ,  H03K19/0185

Abstract: An apparatus is configured to achieve Cpad mitigation effects. The apparatus may include a switch coupled to a current source with first and second states. The apparatus may also include a pad coupled to the switch and having a pad capacitance that charges and discharges based on changes between the first and second switch states. The apparatus may further include a resistor coupled to the switch and the pad, and the resistor is configured to be modulated to reduce the charging or discharging time of the pad.

Abstract translation: 一种装置被配置成实现Cpad缓解效应。 该装置可以包括耦合到具有第一和第二状态的电流源的开关。 该装置还可以包括耦合到开关的焊盘并且具有基于第一和第二开关状态之间的变化而充电和放电的焊盘电容。 该装置还可以包括耦合到开关和焊盘的电阻器，并且电阻器被配置为被调制以减小焊盘的充电或放电时间。

公开(公告)号：US20240113743A1

公开(公告)日：2024-04-04

申请号：US17957053

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Harry Muljono ,  Changhong Lin ,  Mohammad Mamunur Rashid

IPC: H04B3/32

CPC classification number: H04B3/32

Abstract: An improved circuit for generating a crosstalk noise cancellation signal may be used for combining the crosstalk noise cancellation signal with a victim signal without a crosstalk cancelling capacitor. The improved crosstalk cancellation circuit may be used to provide improved TX crosstalk cancellation, and may be used to provide improved performance of increasingly higher speed memory systems regardless of memory process technology, enabling improvements to existing and future memory systems and other communication systems. The improved crosstalk cancellation circuit may include a transmission amplifier to receive a first digital signal and generate a first analog output signal, a crosstalk cancellation circuit to receive the second digital signal and generate an analog cancellation signal, and a first conductive node to generate a first crosstalk canceled signal by combining the first analog output signal with the analog cancellation signal.

公开(公告)号：US20220368122A1

公开(公告)日：2022-11-17

申请号：US17876351

申请日：2022-07-28

Applicant: Intel Corporation

Inventor： Raj Singh Dua ,  Sanjay Joshi ,  Harry Muljono ,  Balkaran Gill

IPC: H02H3/08

Abstract: Analog Front End (AFE) driver or transmitter is used for ESD protection of an input-output (IO) pin, thus reducing ESD diode count and subsequently lowering the pad capacitance to achieve high performance in IO circuits like double data rate (DDR) TO, PCI Express (Peripheral Component Interconnect Express), etc. The channel of active devices that constitute AFE driver are used to connect an IO pad to discharge the ESD current to ground, thus providing an alternative path to ESD current and subsequently reducing the ESD diode count. An additional p-type device (Driver Path Enabler (DPE)) is coupled between the IO pad and a gate terminal of the AFE driver. This additional p-type device triggers the channel of the AFE driver. This p-type device is controlled by an RC based structure which cuts the p-type device off during regular operations when power is ramped-up.

公开(公告)号：US10812075B2

公开(公告)日：2020-10-20

申请号：US16417511

申请日：2019-05-20

Applicant: Intel Corporation

Inventor： Harry Muljono ,  Linda K. Sun ,  Maria Jose Garcia Garcia de Leon ,  Raul Enriquez Shibayama ,  Abraham Isidoro Munoz ,  Carlos Eduardo Lozoya Lopez

IPC: H03K19/00 ,  H03K19/0175 ,  G06F13/40 ,  H04L25/02

Abstract: An apparatus includes a terminal, a first device coupled to the terminal via a first node, the first device to drive a signal on the terminal via the first node, and a second device coupled to the terminal via a second node, wherein the second device comprises a dynamic on-die termination (ODT) circuit coupled to the second node. The dynamic ODT circuit includes: a bus holder circuit to receive the signal from the first device at the second node and select a termination voltage based on the signal, a response delay circuit coupled to the bus holder circuit, the response delay circuit to delay application of the termination voltage to the second node, and a time blanking delay circuit coupled to the bus holder circuit and the response delay circuit to prevent the termination voltage from changing before a threshold period of time elapses.

公开(公告)号：US20160182046A1

公开(公告)日：2016-06-23

申请号：US14581947

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Fengxiang Cai ,  Zibing Yang ,  Harry Muljono

IPC: H03K19/003 ,  H03K5/1534 ,  H03K5/12

CPC classification number: H03K19/00346 ,  H03K5/12 ,  H03K5/1534

Abstract: Embodiments include apparatuses, methods, and systems for crosstalk compensation. In embodiments, a transmitter may include a crosstalk compensation circuit that may receive a victim data signal and one or more attacker data signals. The crosstalk compensation circuit may adjust the timing of transitions in the victim data signal based on detected transitions in the one or more attacker data signals. Other embodiments may be described and claimed.

Abstract translation: 实施例包括用于串扰补偿的装置，方法和系统。 在实施例中，发射机可以包括可以接收受害者数据信号和一个或多个攻击者数据信号的串扰补偿电路。 串扰补偿电路可以基于在一个或多个攻击者数据信号中检测到的转变来调整受害者数据信号中的转换的定时。 可以描述和要求保护其他实施例。