公开(公告)号：US20180293776A1

公开(公告)日：2018-10-11

申请号：US15482677

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： JOYDEEP RAY ,  ABHISHEK R. APPU ,  PATTABHIRAMAN K ,  BALAJI VEMBU ,  ALTUG KOKER ,  NIRANJAN L. COORAY ,  JOSH B. MASTRONARDE

IPC: G06T15/00 ,  G06F9/455 ,  G06F9/48 ,  G06F9/50

Abstract: An apparatus and method are described for allocating local memories to virtual machines. For example, one embodiment of an apparatus comprises: a command streamer to queue commands from a plurality of virtual machines (VMs) or applications, the commands to be distributed from the command streamer and executed by graphics processing resources of a graphics processing unit (GPU); a tile cache to store graphics data associated with the plurality of VMs or applications as the commands are executed by the graphics processing resources; and tile cache allocation hardware logic to allocate a first portion of the tile cache to a first VM or application and a second portion of the tile cache to a second VM or application; the tile cache allocation hardware logic to further allocate a first region in system memory to store spill-over data when the first portion of the tile cache and/or the second portion of the file cache becomes full.

公开(公告)号：US20230177817A1

公开(公告)日：2023-06-08

申请号：US17966067

申请日：2022-10-14

Applicant: Intel Corporation

Inventor： BARNAN DAS ,  MAYURESH M. VARERKAR ,  NARAYAN BISWAL ,  STANLEY J. BARAN ,  GOKCEN CILINGIR ,  NILESH V. SHAH ,  ARCHIE SHARMA ,  SHERINE ABDELHAK ,  PRANEETHA KOTHA ,  NEELAY PANDIT ,  JOHN C. WEAST ,  MIKE B. MACPHERSON ,  DUKHWAN KIM ,  LINDA L. HURD ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  JOYDEEP RAY

IPC: G06V10/82 ,  G06F16/783 ,  G06F16/583 ,  G06V10/94 ,  G06V40/10 ,  G06V40/20 ,  G06F18/2413 ,  G06V10/764

CPC classification number: G06V10/82 ,  G06F16/784 ,  G06F16/5838 ,  G06V10/955 ,  G06V40/10 ,  G06V40/23 ,  G06V40/103 ,  G06F18/24143 ,  G06V10/764

Abstract: A mechanism is described for facilitating recognition, reidentification, and security in machine learning at autonomous machines. A method of embodiments, as described herein, includes facilitating a camera to detect one or more objects within a physical vicinity, the one or more objects including a person, and the physical vicinity including a house, where detecting includes capturing one or more images of one or more portions of a body of the person. The method may further include extracting body features based on the one or more portions of the body, comparing the extracted body features with feature vectors stored at a database, and building a classification model based on the extracted body features over a period of time to facilitate recognition or reidentification of the person independent of facial recognition of the person.

公开(公告)号：US20230029176A1

公开(公告)日：2023-01-26

申请号：US17868448

申请日：2022-07-19

Applicant: Intel Corporation

Inventor： JOYDEEP RAY ,  ARAVINDH ANANTARAMAN ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  ELMOUSTAPHA OULD-AHMED-VALL ,  VALENTIN ANDREI ,  SUBRAMANIAM MAIYURAN ,  NICOLAS GALOPPO VON BORRIES ,  VARGHESE GEORGE ,  MIKE MACPHERSON ,  BEN ASHBAUGH ,  MURALI RAMADOSS ,  VIKRANTH VEMULAPALLI ,  WILLIAM SADLER ,  JONATHAN PEARCE ,  SUNGYE KIM

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/38 ,  G06T15/00

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210201556A1

公开(公告)日：2021-07-01

申请号：US17141431

申请日：2021-01-05

Applicant: Intel Corporation

Inventor： JOYDEEP RAY ,  ABHISHEK R. APPU ,  PATTABHIRAMAN K ,  BALAJI VEMBU ,  ALTUG KOKER ,  NIRANJAN L. COORAY ,  JOSH B. MASTRONARDE

IPC: G06T15/00 ,  G06F9/455 ,  G06T1/60 ,  G09G5/36 ,  G09G5/00 ,  G09G5/393 ,  G06F9/48 ,  G06F9/50

Abstract: An apparatus and method are described for allocating local memories to virtual machines. For example, one embodiment of an apparatus comprises: a command streamer to queue commands from a plurality of virtual machines (VMs) or applications, the commands to be distributed from the command streamer and executed by graphics processing resources of a graphics processing unit (GPU); a tile cache to store graphics data associated with the plurality of VMs or applications as the commands are executed by the graphics processing resources; and tile cache allocation hardware logic to allocate a first portion of the tile cache to a first VM or application and a second portion of the tile cache to a second VM or application; the tile cache allocation hardware logic to further allocate a first region in system memory to store spill-over data when the first portion of the tile cache and/or the second portion of the file cache becomes full.

公开(公告)号：US20210041934A1

公开(公告)日：2021-02-11

申请号：US17080395

申请日：2020-10-26

Applicant: Intel Corporation

Inventor： KINCHIT DESAI ,  SANJEEV JAHAGIRDAR ,  PRASOONKUMAR SURTI ,  JOYDEEP RAY

IPC: G06F1/3237 ,  G06N3/04 ,  G06N3/08 ,  G06F1/3234 ,  G06F1/3206

Abstract: Embodiments are generally directed to providing power savings for a neural network architecture with zero activations during inference. An embodiment of an apparatus includes one or more processors including one or more processor cores; and a memory to store data for processing including neural network processing, wherein the apparatus to perform a fast clear operation to initialize activation buffers for a neural network by updating metadata to indicate zero values, the neural network including a plurality of layers, wherein the apparatus is to compare outputs for the neural network to the metadata values and to write an output to memory only if the output is non-zero.

公开(公告)号：US20200218539A1

公开(公告)日：2020-07-09

申请号：US16243663

申请日：2019-01-09

Applicant: Intel Corporation

Inventor： JAMES VALERIO ,  VASANTH RANGANATHAN ,  JOYDEEP RAY ,  PRADEEP RAMANI

IPC: G06F9/38 ,  G06F13/28 ,  G06T1/20

Abstract: A graphics processing device comprises a set of compute units to execute multiple threads of a workload, a cache coupled with the set of compute units, and a prefetcher to prefetch instructions associated with the workload. The prefetcher is configured to use a thread dispatch command that is used to dispatch threads to execute a kernel to prefetch instructions, parameters, and/or constants that will be used during execution of the kernel. Prefetch operations for the kernel can then occur concurrently with thread dispatch operations.

公开(公告)号：US20190318550A1

公开(公告)日：2019-10-17

申请号：US16383849

申请日：2019-04-15

Applicant: Intel Corporation

Inventor： BARATH LAKSHAMANAN ,  LINDA l. HURD ,  BEN J. ASHBAUGH ,  ELMOUSTAPHA OULD-AHMED-VALL ,  LIWEI MA ,  JINGYI JIN ,  JUSTIN E. GOTTSCHLICH ,  CHANDRASEKARAN SAKTHIVEL ,  MICHAEL S. STRICKLAND ,  BRIAN T. LEWIS ,  LINDSEY KUPER ,  ALTUG KOKER ,  ABHISHEK R. APPU ,  PRASOONKUMAR SURTI ,  JOYDEEP RAY ,  BALAJI VEMBU ,  JAVIER S. TUREK ,  NAILA FAROOQUI

IPC: G07C5/00 ,  G06F9/50 ,  H04W28/08 ,  B60W30/00 ,  H04L29/08 ,  G01C21/34 ,  G05D1/00 ,  G08G1/01 ,  G06N20/00

Abstract: One embodiment provides for a computing device within an autonomous vehicle, the compute device comprising a wireless network device to enable a wireless data connection with an autonomous vehicle network, a set of multiple processors including a general-purpose processor and a general-purpose graphics processor, the set of multiple processors to execute a compute manager to manage execution of compute workloads associated with the autonomous vehicle, the compute workload associated with autonomous operations of the autonomous vehicle, and offload logic configured to execute on the set of multiple processors, the offload logic to determine to offload one or more of the compute workloads to one or more autonomous vehicles within range of the wireless network device.

公开(公告)号：US20190318446A1

公开(公告)日：2019-10-17

申请号：US16365056

申请日：2019-03-26

Applicant: Intel Corporation

Inventor： JOYDEEP RAY ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  BALAJI VEMBU

IPC: G06T1/20 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888 ,  G06T1/60 ,  G06F12/0811 ,  G06F12/0875

Abstract: An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, an apparatus comprises a processor comprising one or more cores, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (GPU) to execute graphics instructions and process graphics data, wherein the GPU and processor cores are to share a virtual address space for accessing a system memory; a GPU memory addressable through the virtual address space shared by the processor cores and GPU; and bias management circuitry to store an indication for whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, the data is to be accessed by the GPU without necessarily accessing the processor's cache coherence controllers.

公开(公告)号：US20180300556A1

公开(公告)日：2018-10-18

申请号：US15488555

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： MAYURESH M. VARERKAR ,  BARNAN DAS ,  NARAYAN BISWAL ,  STANLEY J. BARAN ,  GOKCEN CILINGIR ,  NILESH V. SHAH ,  ARCHIE SHARMA ,  SHERINE ABDELHAK ,  SACHIN GODSE ,  FARSHAD AKHBARI ,  NARAYAN SRINIVASA ,  ALTUG KOKER ,  NADATHUR RAJAGOPALAN SATISH ,  DUKHWAN KIM ,  FENG CHEN ,  ABHISHEK R. APPU ,  JOYDEEP RAY ,  PING T. TANG ,  MICHAEL S. STRICKLAND ,  XIAOMING CHEN ,  ANBANG YAO ,  TATIANA SHPEISMAN ,  Vasanth Ranganathan ,  Sanjeev Jahagirdir

IPC: G06K9/00 ,  G06T1/20

CPC classification number: G06K9/00771 ,  G06K9/00362 ,  G06K9/00711 ,  G06K2009/00738 ,  G06T1/20

Abstract: A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data.

公开(公告)号：US20210089301A1

公开(公告)日：2021-03-25

申请号：US16582406

申请日：2019-09-25

Applicant: Intel Corporation

Inventor： SUBRAMANIAM MAIYURAN ,  VARGHESE GEORGE ,  JOYDEEP RAY ,  ASHUTOSH GARG ,  JORGE PARRA ,  SHUBH SHAH ,  SHUBRA MARWAHA

IPC: G06F9/30 ,  G06F17/16 ,  G06F9/50

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a shared local memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive an instruction to initiate a matrix multiplication operation, write a first set of matrix data into a first set of registers, and share the first set of matrix data between the first processing resource and the second processing resource for use in the matrix multiplication operation. Other embodiments may be described and claimed.