公开(公告)号：US08819306B2

公开(公告)日：2014-08-26

申请号：US13729673

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David Lee

IPC: G06F13/00

CPC classification number: H04L47/10 ,  G06F5/06 ,  G06F13/124 ,  G06F13/385 ,  G06F13/4059 ,  G06F13/42 ,  G06F13/4221 ,  G06F13/4252 ,  G06F13/4265 ,  G06F13/4269 ,  G06F13/4282 ,  H04L47/30

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

Abstract translation: 提出了一种增强的通用输入/输出通信架构，协议和相关方法。

公开(公告)号：US20140189174A1

公开(公告)日：2014-07-03

申请号：US14144320

申请日：2013-12-30

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David Lee

IPC: G06F13/42

CPC classification number: H04L47/10 ,  G06F5/06 ,  G06F13/124 ,  G06F13/385 ,  G06F13/4059 ,  G06F13/42 ,  G06F13/4221 ,  G06F13/4252 ,  G06F13/4265 ,  G06F13/4269 ,  G06F13/4282 ,  H04L47/30

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

Abstract translation: 提出了一种增强的通用输入/输出通信架构，协议和相关方法。

公开(公告)号：US09736276B2

公开(公告)日：2017-08-15

申请号：US14310164

申请日：2014-06-20

Applicant: INTEL CORPORATION

Inventor： Mahesh Wagh ,  Abhishek Singhal ,  Jasmin Ajanovic

IPC: H04L29/06 ,  G06F13/38

CPC classification number: H04L69/22 ,  G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: In one embodiment, the present invention includes a fabric on a first semiconductor die to communicate with at least one agent on the die according to an on-chip protocol and a packetization layer coupled to the fabric to receive command and data information from the fabric on multiple links and to packetize the information into a packet for transmission from the die to another die via an in-package packetized link. Other embodiments are described and claimed.

公开(公告)号：US09736071B2

公开(公告)日：2017-08-15

申请号：US14580073

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David Lee

IPC: G06F3/00 ,  H04L12/801 ,  G06F13/12 ,  G06F13/38 ,  G06F13/42 ,  G06F13/40 ,  G06F5/06 ,  H04L12/835

CPC classification number: H04L47/10 ,  G06F5/06 ,  G06F13/124 ,  G06F13/385 ,  G06F13/4059 ,  G06F13/42 ,  G06F13/4221 ,  G06F13/4252 ,  G06F13/4265 ,  G06F13/4269 ,  G06F13/4282 ,  H04L47/30

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

公开(公告)号：US09602408B2

公开(公告)日：2017-03-21

申请号：US14144320

申请日：2013-12-30

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David Lee

IPC: G06F15/16 ,  H04L12/801 ,  G06F13/12 ,  G06F13/38 ,  G06F13/42 ,  G06F13/40 ,  G06F5/06

CPC classification number: H04L47/10 ,  G06F5/06 ,  G06F13/124 ,  G06F13/385 ,  G06F13/4059 ,  G06F13/42 ,  G06F13/4221 ,  G06F13/4252 ,  G06F13/4265 ,  G06F13/4269 ,  G06F13/4282 ,  H04L47/30

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

公开(公告)号：US09442855B2

公开(公告)日：2016-09-13

申请号：US14583601

申请日：2014-12-27

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC: G06F3/00 ,  G06F13/14 ,  G06F12/08 ,  G06F1/32 ,  H04L12/66 ,  G06F13/40 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US09071528B2

公开(公告)日：2015-06-30

申请号：US13730024

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David Lee

IPC: G06F15/16 ,  H04L12/801 ,  G06F13/12 ,  G06F13/38 ,  G06F13/42 ,  G06F13/40

CPC classification number: H04L47/10 ,  G06F5/06 ,  G06F13/124 ,  G06F13/385 ,  G06F13/4059 ,  G06F13/42 ,  G06F13/4221 ,  G06F13/4252 ,  G06F13/4265 ,  G06F13/4269 ,  G06F13/4282 ,  H04L47/30

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

公开(公告)号：US08806068B2

公开(公告)日：2014-08-12

申请号：US13706575

申请日：2012-12-06

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC: G06F3/00 ,  G06F5/00

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

公开(公告)号：US10360171B2

公开(公告)日：2019-07-23

申请号：US14799165

申请日：2015-07-14

Applicant: Intel Corporation

Inventor： David Harriman ,  Jasmin Ajanovic

IPC: G06F13/42 ,  H04L29/06 ,  G06F13/40 ,  G06F11/07

Abstract: A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages. The group of messages to include a message to unlock a logical device, a message to reset a logical device, a message to indicate a correctable error condition, a message to indicate an uncorrectable error condition, a message to indicate a fatal error condition, a message to report a bad request packet, a message to indicate power management and a message to emulate an interrupt signal.

公开(公告)号：US09860173B2

公开(公告)日：2018-01-02

申请号：US14145376

申请日：2013-12-31

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David M. Lee

IPC: G06F15/16 ,  H04L12/801 ,  G06F13/12 ,  G06F13/38 ,  G06F13/42 ,  G06F13/40 ,  G06F5/06 ,  H04L12/835

CPC classification number: H04L47/10 ,  G06F5/06 ,  G06F13/124 ,  G06F13/385 ,  G06F13/4059 ,  G06F13/42 ,  G06F13/4221 ,  G06F13/4252 ,  G06F13/4265 ,  G06F13/4269 ,  G06F13/4282 ,  H04L47/30

Abstract: A storage device is provided to maintain a count of flow control credits to be granted to a device in association with transactions over a channel to be implemented on a data link and control logic is provided to communicate, to the device, an indication of an amount of flow control credits for the device in association with a reset of the data link.