公开(公告)号：US20240329129A1

公开(公告)日：2024-10-03

申请号：US18537076

申请日：2023-12-12

Applicant: Intel Corporation

Inventor： Sridhar Muthrasanallur ,  Debendra Das Sharma ,  Swadesh Choudhary ,  Gerald Pasdast ,  Peter Onufryk

IPC: G01R31/317 ,  G06F11/27 ,  G06F13/42

CPC classification number: G01R31/31705 ,  G06F11/27 ,  G06F13/4221 ,  G06F2213/0026

Abstract: Technologies for a unified debug and test architecture in chiplets is disclosed. In an illustrative embodiment, several chiplets are integrated on an integrated circuit package. The chiplets are connected by a package interconnect, such as a universal chiplet interconnect express (UCIe) interconnect. Each chiplet includes several debug nodes, which are connected by an on-chiplet network. One of the chiplets, referred to as a package debug endpoint, acts as a link endpoint for an off-package link, such as a peripheral component interconnect express (PCIe) link. In use, debug messages can be sent to the package debug endpoint over a PCIe link. The debug messages can be routed within the chiplets and between chiplets, allowing for the debug functionality at each debug node to be probed using a common protocol. In this manner, chiplets from different vendors can be integrated into the same package and tested using common software.

公开(公告)号：US20240111701A1

公开(公告)日：2024-04-04

申请号：US18539063

申请日：2023-12-13

Applicant: Intel Corporation

Inventor： Aruni P. Nelson ,  Enrico David Carrieri ,  Rolf Kuehnis ,  Peter Onufryk ,  Sridhar Muthrasanallur

IPC: G06F13/40 ,  G06F13/22 ,  G06F13/42

CPC classification number: G06F13/4031 ,  G06F13/225 ,  G06F13/4221

Abstract: Embodiments herein relate to a universal component interconnect express (UCIe) link that includes a mainband and a sideband. One or more pieces of logic may identify a data that is to be transmitted on the sideband. The logic may then identify, based on factors such as a characteristic of the data or a characteristic of the link, whether to transmit the data on the mainband. Other embodiments may be described and/or claimed.

公开(公告)号：US09026682B2

公开(公告)日：2015-05-05

申请号：US13713635

申请日：2012-12-13

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC: G06F3/00 ,  G06F12/08 ,  G06F1/32 ,  H04L12/66 ,  G06F13/40 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US11514551B2

公开(公告)日：2022-11-29

申请号：US17032788

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Yogesh Vikram Marathe ,  Ankitkumar Pravinbhai Navik ,  Praveen Diwakar ,  Tvrtko Ursulin ,  Sridhar Muthrasanallur ,  Aravindan Muthukumar ,  Kedar J. Karanje ,  Sujith Thomas ,  Vipin Anand

IPC: G06T1/20 ,  G06F9/32 ,  G06F12/0804 ,  G06F9/48 ,  G06F9/38

Abstract: A system may include a graphics processing unit including a command counter. The system may also include a general-purpose processor to: in response to a detection of a timing signal, determine a count value of the command counter included in the graphics processing unit; determine a first threshold range of a plurality of threshold ranges that matches the determined count value of the command counter; select, based on the determined first threshold range, a first configuration profile of a plurality of configuration profiles for the graphics processing unit; and cause the graphics processing unit to use the selected first configuration profile. Other embodiments are described and claimed.

公开(公告)号：US20210405892A1

公开(公告)日：2021-12-30

申请号：US17116991

申请日：2020-12-09

Applicant: Intel Corporation

Inventor： Nadav Bonen ,  Sridhar Muthrasanallur ,  Srinivas Pandruvada ,  Vishwanath Somayaji ,  Prashant Kodali

IPC: G06F3/06

Abstract: Logical memory is divided into two regions. Data in the first region is always retained. The first region of memory is designated online (or powered on) and is not offlined during standby or low power mode. The second region is the rest of the memory which can be potentially placed in non-self-refresh mode during standby by offlining the memory region. Content in the second region can be moved to the first region or can be flushed to another memory managed by the operating system. When the first region does not have enough space to accommodate data from the second region, the operating system can increase the logical size of the first region. Retaining the content of the first region by putting that region in self-refresh and saving power in the second region by not putting it in self-refresh is performed by an improved Partial Array Self Refresh scheme.

公开(公告)号：US09892069B2

公开(公告)日：2018-02-13

申请号：US14800419

申请日：2015-07-15

Applicant: Intel Corporation

Inventor： Rajesh Sankaran Madukkarumukumana ,  Gilbert Neiger ,  Ohad Falik ,  Sridhar Muthrasanallur ,  Gideon Gerzon

IPC: G06F13/24 ,  G06F9/48

CPC classification number: G06F13/24 ,  G06F9/4812

Abstract: Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.

公开(公告)号：US09575895B2

公开(公告)日：2017-02-21

申请号：US14609620

申请日：2015-01-30

Applicant: Intel Corporation

Inventor： Yen-Cheng Liu ,  Robert G. Blankenship ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Kenneth C. Creta ,  Sridhar Muthrasanallur ,  Bahaa Fahim

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0815 ,  G06F12/0831 ,  G06F2212/452 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有多个核心的多核处理器，共享高速缓存存储器，用于在多核处理器与耦合到多核处理器的至少一个IO设备之间进行接口的集成输入/输出（IIO）模块，以及 高速缓存代理以对多个核和IIO模块执行高速缓存一致性操作。 描述和要求保护其他实施例。

公开(公告)号：US09116869B2

公开(公告)日：2015-08-25

申请号：US14467604

申请日：2014-08-25

Applicant: Intel Corporation

Inventor： Rajesh Sankaran Madukkarumukumana ,  Gilbert Neiger ,  Ohad Falik ,  Sridhar Muthrasanallur ,  Gideon Gerzon

IPC: G06F13/24 ,  G06F9/48

CPC classification number: G06F13/24 ,  G06F9/4812

Abstract: Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.

Abstract translation: 公开了向虚拟处理器发布中断的系统，装置和方法的实施例。 在一个实施例中，装置包括查找逻辑和发布逻辑。 查找逻辑是在数据结构中查找与中断请求相关联的条目给虚拟处理器。 发布逻辑是将中断请求发布在由第一数据结构中的信息指定的数据结构中。

公开(公告)号：US20150205736A1

公开(公告)日：2015-07-23

申请号：US14565718

申请日：2014-12-10

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Rajesh Sankaran Madukkarumukumana ,  Richard A. Uhlig ,  Udo Steinberg ,  Sebastian Schoenberg ,  Sridhar Muthrasanallur ,  Steven M. Bennett ,  Andrew V. Anderson ,  Erik C. Cota-Robles

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F9/45533 ,  G06F9/4812

Abstract: Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.

Abstract translation: 公开了用于向虚拟处理器递送中断的装置，方法和系统的实施例。 在一个实施例中，装置包括用于接收中断请求，传递逻辑和退出逻辑的接口。 交付逻辑是基于中断请求的属性来确定中断请求是否被传送到虚拟处理器。 如果传递逻辑确定中断请求不被传送到虚拟处理器，则出口逻辑是将控制传送到主机。

公开(公告)号：US20150143051A1

公开(公告)日：2015-05-21

申请号：US14609620

申请日：2015-01-30

Applicant: Intel Corporation

Inventor： Yen-Cheng Liu ,  Robert G. Blankenship ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Kenneth C. Creta ,  Sridhar Muthrasanallur ,  Bahaa Fahim

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0815 ,  G06F12/0831 ,  G06F2212/452 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有多个核心的多核处理器，共享高速缓存存储器，用于在多核处理器与耦合到多核处理器的至少一个IO设备之间进行接口的集成输入/输出（IIO）模块，以及 高速缓存代理以对多个核和IIO模块执行高速缓存一致性操作。 描述和要求保护其他实施例。