公开(公告)号：US20230086881A1

公开(公告)日：2023-03-23

申请号：US17481247

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Whitney BRYKS ,  Jieying KONG ,  Bainye Francoise ANGOUA ,  Junxin WANG ,  Sarah BLYTHE ,  Ala OMER ,  Dilan SENEVIRATNE

IPC: G02B6/43 ,  G02B6/42

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to a double-sided glass substrate, to which a PIC is hybrid bonded to a first side of the glass substrate. A die is coupled with the second side of the glass substrate opposite the first side, the PIC and the die are electrically coupled with electrically conductive through glass vias that extend from the first side of the glass substrate to the second side of the glass substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US20240222089A1

公开(公告)日：2024-07-04

申请号：US18090400

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Ala OMER ,  Peumie ABEYRATNE KURAGAMA ,  Jieying KONG ,  Wendy LIN ,  Ao WANG

IPC: H01J37/32 ,  H01L21/3105

CPC classification number: H01J37/32715 ,  H01L21/31058 ,  H01J2237/2007 ,  H01J2237/20235 ,  H01J2237/334 ,  H01J2237/3355 ,  H01J2237/336 ,  H01L21/02063

Abstract: This disclosure describes designs and methods for via cleaning, peeling protective film, and providing mild surface roughening and cleaning of a computer chip. A system may include a first electrode configured to generate plasma associated with cleaning vias by etching a residual material associated with smearing; an electrostatic stage configured to generate an electrostatic force associated with peeling the dielectric protective film from the semiconductor; and a stage on which the semiconductor is positioned while the electrostatic stage peels the dielectric protective film from the semiconductor, wherein the plasma is further associated with roughening a surface of the semiconductor after peeling the dielectric protective film from the semiconductor.

公开(公告)号：US20230405976A1

公开(公告)日：2023-12-21

申请号：US18241067

申请日：2023-08-31

Applicant: Intel Corporation

Inventor： Jieying KONG ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Patrick QUACH ,  Dilan SENEVIRATNE

IPC: B32B17/10 ,  B32B15/20 ,  H01L23/00 ,  H01L23/48

CPC classification number: B32B17/10192 ,  B32B15/20 ,  H01L24/09 ,  H01L23/481 ,  H01L2224/02379

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to a manufacturing process flow for packages that include one or more glass layers that include patterning features, such as electrically conductive traces, RDLs, and vias within the packages. In embodiments, a package may include a glass layer with a first side and a second side opposite the first side, where the glass layer is a dielectric layer. The package may include another layer coupled with the first side of the glass layer, and a pattern on the second side of the glass layer to receive a deposited material in at least a portion of the pattern.

公开(公告)号：US20230091834A1

公开(公告)日：2023-03-23

申请号：US17482380

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Bainye Francoise ANGOUA ,  Ala OMER ,  Sarah BLYTHE ,  Junxin WANG ,  Whitney BRYKS ,  Dilan SENEVIRATNE ,  Jieying KONG

IPC: G02B6/125 ,  G02B6/13

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed an optical waveguide formed in a glass layer. The optical waveguide may be formed by creating a first trench extending from a surface of the glass layer, and then creating a second trench extending from the bottom of the first trench, then subsequently filling the trenches with a core material which may then be topped with a cladding material. Other embodiments may be described and/or claimed.

公开(公告)号：US20210125912A1

公开(公告)日：2021-04-29

申请号：US16666202

申请日：2019-10-28

Applicant: Intel Corporation

Inventor： Zhiguo QIAN ,  Gang DUAN ,  Kemal AYGÜN ,  Jieying KONG ,  Brandon C. MARIN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/66

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a first buildup layer and a second buildup layer over the first buildup layer. In an embodiment, a void is disposed through the second buildup layer. In an embodiment the electronic package further comprises a first pad over the second buildup layer. In an embodiment, the first pad covers the void.

公开(公告)号：US20210050289A1

公开(公告)日：2021-02-18

申请号：US16539254

申请日：2019-08-13

Applicant: Intel Corporation

Inventor： Jieying KONG ,  Srinivas PIETAMBARAM ,  Gang DUAN

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/64

Abstract: Embodiments disclosed herein include hybrid cores for electronic packaging applications. In an embodiment, a package substrate comprises a plurality of glass layers and a plurality of dielectric layers. In an embodiment, the glass layers alternate with the dielectric layers. In an embodiment, a through-hole through the plurality of glass layers and the plurality of dielectric layers is provided. In an embodiment a conductive through-hole via is disposed in the through-hole.