公开(公告)号：US20250013507A1

公开(公告)日：2025-01-09

申请号：US18891976

申请日：2024-09-20

Applicant: Intel Corporation

Inventor： Chris M. MacNamara ,  John J. Browne ,  Przemyslaw J. Perycz ,  Pawel S. Zak ,  Reshma Pattan

IPC: G06F9/50 ,  G06F1/26 ,  G06F9/48

Abstract: Techniques for computer power management are disclosed. In one embodiment, a data center includes several compute nodes and a power management node. Power telemetry data is gathered at each of the compute nodes and sent to the power management node. The power management node analyzes the telemetry data, such as by applying filtering to identify certain metrics. The power management node may use rules to analyze the telemetry data and determine whether power management actions should be performed. The power management node may instruct the compute node to, e.g., change a power state of a processor or processor core. In some embodiments, cores may be managed by an orchestrator, and the orchestrator may identify cores to be placed in high-power and low-power states, as appropriate.

公开(公告)号：US12177277B2

公开(公告)日：2024-12-24

申请号：US17313353

申请日：2021-05-06

Applicant: Intel Corporation

Inventor： Lokpraveen Mosur ,  Ilango Ganga ,  Robert Cone ,  Kshitij Arun Doshi ,  John J. Browne ,  Mark Debbage ,  Stephen Doyle ,  Patrick Fleming ,  Doddaballapur Jayasimha

IPC: H04L65/61 ,  H04L47/50 ,  H04L49/9005

Abstract: In one embodiment, a system includes a device and a host. The device includes a device stream buffer. The host includes a processor to execute at least a first application and a second application, a host stream buffer, and a host scheduler. The first application is associated with a first transmit streaming channel to stream first data from the first application to the device stream buffer. The first transmit streaming channel has a first allocated amount of buffer space in the device stream buffer. The host scheduler schedules enqueue of the first data from the first application to the first transmit streaming channel based at least in part on availability of space in the first allocated amount of buffer space in the device stream buffer. Other embodiments are described and claimed.

公开(公告)号：US12132825B2

公开(公告)日：2024-10-29

申请号：US17561558

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Timothy Verrall ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Karthik Kumar ,  Ned M. Smith ,  Rajesh Poornachandran ,  Kapil Sood ,  Tarun Viswanathan ,  John J. Browne ,  Patrick Kutch

IPC: H04L9/08

CPC classification number: H04L9/083 ,  H04L9/0836 ,  H04L9/0891 ,  H04L9/0894 ,  H04L9/0897

Abstract: Technologies for accelerated key caching in an edge hierarchy include multiple edge appliance devices organized in tiers. An edge appliance device receives a request for a key, such as a private key. The edge appliance device determines whether the key is included in a local key cache and, if not, requests the key from an edge appliance device included in an inner tier of the edge hierarchy. The edge appliance device may request the key from an edge appliance device included in a peer tier of the edge hierarchy. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys in the key cache for eviction. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys for pre-fetching. Those functions of the edge appliance device may be performed by an accelerator such as an FPGA. Other embodiments are described and claimed.

公开(公告)号：US12066853B2

公开(公告)日：2024-08-20

申请号：US18329492

申请日：2023-06-05

Applicant: Intel Corporation

Inventor： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris MacNamara ,  John J. Browne ,  Ripan Das

IPC: G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/30 ,  G06F9/455

CPC classification number: G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/30101 ,  G06F9/45558 ,  G06F2009/45591 ,  Y02D10/00

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US20240152460A1

公开(公告)日：2024-05-09

申请号：US18545933

申请日：2023-12-19

Applicant: Intel Corporation

Inventor： John J. Browne ,  Kshitij Arun Doshi ,  Thijs Metsch ,  Francesc Guim Bernat ,  Adrian Hoban

IPC: G06F12/0842

CPC classification number: G06F12/0842

Abstract: An example disclosed apparatus comprises a trigger monitor to detect an event satisfying a cache scrape trigger rule during execution of a workload, and a cache scraper to scrape cache data from cache in hardware during the execution of the workload.

公开(公告)号：US20240031219A1

公开(公告)日：2024-01-25

申请号：US18478514

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： John J. Browne ,  Kshitij Arun Doshi ,  Francesc Guim Bernat ,  Adrian Hoban ,  Mats Agerstam ,  Shekar Ramachandran ,  Thijs Metsch ,  Timothy Verrall ,  Ciara Loftus ,  Emma Collins ,  Krzysztof Kepka ,  Pawel Zak ,  Aibhne Breathnach ,  Ivens Zambrano ,  Shanshu Yang

IPC: H04L41/0654 ,  H04L41/0806

CPC classification number: H04L41/0654 ,  H04L41/0806

Abstract: Methods, apparatus, and systems are disclosed for mapping active assurance intents to resource orchestration and life cycle management. An example apparatus disclosed herein is to reserve a probe on a compute device in a cluster of compute devices based on a request to satisfy a resource availability criterion associated with a resource of the cluster, apply a risk mitigation operation based on the resource availability criterion before deployment of a workload to the cluster, and monitor whether the criterion is satisfied based on data from the probe after deployment of the workload to the cluster.

公开(公告)号：US20230379271A1

公开(公告)日：2023-11-23

申请号：US18228420

申请日：2023-07-31

Applicant: Intel Corporation

Inventor： Ren Wang ,  Mia PRIMORAC ,  Tsung-Yuan C. Tai ,  Saikrishna EDUPUGANTI ,  John J. Browne

IPC: H04L49/90 ,  H04L47/36

CPC classification number: H04L49/9068 ,  H04L47/365 ,  H04L49/9005

Abstract: Technologies for dynamically managing a batch size of packets include a network device. The network device is to receive, into a queue, packets from a remote node to be processed by the network device, determine a throughput provided by the network device while the packets are processed, determine whether the determined throughput satisfies a predefined condition, and adjust a batch size of packets in response to a determination that the determined throughput satisfies a predefined condition. The batch size is indicative of a threshold number of queued packets required to be present in the queue before the queued packets in the queue can be processed by the network device.

公开(公告)号：US20230315143A1

公开(公告)日：2023-10-05

申请号：US18329492

申请日：2023-06-05

Applicant: Intel Corporation

Inventor： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris MacNamara ,  John J. Browne ,  Ripan Das

IPC: G06F1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455 ,  G06F1/324

CPC classification number: G06F1/08 ,  G06F1/3203 ,  G06F9/30101 ,  G06F9/45558 ,  G06F1/324 ,  G06F2009/45591

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US20230273597A1

公开(公告)日：2023-08-31

申请号：US18313994

申请日：2023-05-08

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Amruta Misra ,  Kshitij Arun Doshi ,  John J. Browne ,  Marcos Carranza

IPC: G05B19/416

CPC classification number: G05B19/416 ,  G05B2219/49216

Abstract: Telemetry systems for monitoring cooling of compute components and related apparatus and methods are disclosed. An example apparatus includes interface circuitry, machine-readable instructions, and programmable circuitry to at least one of instantiate or execute the machine-readable instructions to generate a heatmap based on outputs of one or more sensors in an environment, the environment including a first compute device, the sensor outputs including a metric associated with a property of a coolant and a location of the sensor in the environment, identify a compute performance metric of the first compute device, determine a cooling parameter for the first compute device based on the heatmap and the compute performance metric, and cause a cooling distribution unit to control flow of the coolant in the environment based on the cooling parameter.

公开(公告)号：US11703933B2

公开(公告)日：2023-07-18

申请号：US16747202

申请日：2020-01-20

Applicant: Intel Corporation

Inventor： Liang Ma ,  Weigang Li ,  Madhusudana Raghupatruni ,  Hongjun Ni ,  Xuekun Hu ,  Changzheng Wei ,  Chris MacNamara ,  John J. Browne

IPC: G06F9/54 ,  G06F1/324 ,  G06F21/60 ,  G06F21/53

CPC classification number: G06F1/324 ,  G06F9/544 ,  G06F21/53 ,  G06F21/606 ,  G06F2221/032

Abstract: Examples described herein provide for a first core to map a measurement of packet processing activity and operating parameters so that a second core can access the measurement of packet processing activity and potentially modify an operating parameter of the first core. The second core can modify operating parameters of the first core based on the measurement of packet processing activity. The first and second cores can be provisioned on start-up with a common key. The first and second cores can use the common key to encrypt or decrypt measurement of packet processing activity and operating parameters that are shared between the first and second cores. Accordingly, operating parameters of the first core can be modified by a different core while providing for secure modification of operating parameters.