公开(公告)号：US12236243B2

公开(公告)日：2025-02-25

申请号：US18138591

申请日：2023-04-24

Applicant: Intel Corporation

Inventor： Jason W. Brandt ,  Deepak K. Gupta ,  Rodrigo Branco ,  Joseph Nuzman ,  Robert S. Chappell ,  Sergiu Ghetie ,  Wojciech Powiertowski ,  Jared W. Stark, IV ,  Ariel Sabba ,  Scott J. Cape ,  Hisham Shafi ,  Lihu Rappoport ,  Yair Berger ,  Scott P. Bobholz ,  Gilad Holzstein ,  Sagar V. Dalvi ,  Yogesh Bijlani

IPC: G06F9/38 ,  G06F9/30

Abstract: Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.

公开(公告)号：US20230418934A1

公开(公告)日：2023-12-28

申请号：US17849351

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Scott D. Constable ,  Joao Batista Correa Gomes Moreira ,  Alyssa A. Milburn ,  Ke Sun ,  Michael LeMay ,  David M. Durham ,  Joseph Nuzman ,  Jason W. Brandt ,  Anders Fogh

IPC: G06F21/54 ,  G06F21/51

CPC classification number: G06F21/54 ,  G06F21/51 ,  G06F2221/033

Abstract: In one embodiment, an indirect branch is detected in computer program code. The indirect branch calls one of a plurality of functions using a first register. In response, the computer program code is augmented to store an identifier of the indirect branch call in a second register, and the code for each of the plurality of functions is augmented to: determine whether an identifier for the function matches the identifier stored in the second register and render the first register unusable if the identifier for the function does not match the identifier stored in the second register.

公开(公告)号：US20230273846A1

公开(公告)日：2023-08-31

申请号：US18313905

申请日：2023-05-08

Applicant: Intel Corporation

Inventor： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

IPC: G06F11/07 ,  G06F12/00 ,  G06F9/38 ,  G06F12/109 ,  G06F21/60

CPC classification number: G06F11/0751 ,  G06F11/073 ,  G06F12/00 ,  G06F9/38 ,  G06F12/109 ,  G06F21/60 ,  G06F12/145

Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

公开(公告)号：US11675594B2

公开(公告)日：2023-06-13

申请号：US16236049

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Robert S. Chappell ,  Jason W. Brandt ,  Alan Cox ,  Asit Mallick ,  Joseph Nuzman ,  Arjan Van De Ven

IPC: G06F9/30 ,  G06F9/38 ,  G06F21/55

CPC classification number: G06F9/3842 ,  G06F9/30058 ,  G06F9/30145 ,  G06F21/556 ,  G06F2221/033

Abstract: Embodiments of instructions are detailed herein including one or more of 1) a branch fence instruction, prefix, or variants (BFENCE); 2) a predictor fence instruction, prefix, or variants (PFENCE); 3) an exception fence instruction, prefix, or variants (EFENCE); 4) an address computation fence instruction, prefix, or variants (AFENCE); 5) a register fence instruction, prefix, or variants (RFENCE); and, additionally, modes that apply the above semantics to some or all ordinary instructions.

公开(公告)号：US20220207147A1

公开(公告)日：2022-06-30

申请号：US17134343

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Carlos Rozas ,  Fangfei Liu ,  Xiang Zou ,  Francis McKeen ,  Jason W. Brandt ,  Joseph Nuzman ,  Alaa Alameldeen ,  Abhishek Basak ,  Scott Constable ,  Thomas Unterluggauer ,  Asit Mallick ,  Matthew Fernandez

IPC: G06F21/57 ,  G06F21/54 ,  G06F9/30

Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and execution circuitry coupled to the decode circuitry. The decode circuitry is to decode a register hardening instruction to mitigate vulnerability to a speculative execution attack. The execution circuitry is to be hardened in response to the register hardening instruction.

公开(公告)号：US11238155B2

公开(公告)日：2022-02-01

申请号：US16456578

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Robert S. Chappell ,  Jared W. Stark, IV ,  Joseph Nuzman ,  Stephen Robinson ,  Jason W. Brandt

IPC: G06F9/30 ,  G06F9/38 ,  G06F21/55 ,  G06F21/62 ,  G06F9/48 ,  G06F12/0802

Abstract: Systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. In one embodiment, a processor includes a core having a plurality of physical contexts to execute a plurality of threads, a plurality of structures shared by the plurality of threads, a context mapping structure to map context signatures to respective physical contexts of the plurality of physical contexts, each physical context to identify and differentiate state of the plurality of structures, and a context manager circuit to, when one or more of a plurality of fields that comprise a context signature is changed, search the context mapping structure for a match to another context signature, and when the match is found, a physical context associated with the match is set as an active physical context for the core.

公开(公告)号：US10976961B2

公开(公告)日：2021-04-13

申请号：US16228374

申请日：2018-12-20

Applicant: Intel Corporation

Inventor： Ron Gabor ,  Tomer Stark ,  Joseph Nuzman ,  Ady Tal

IPC: G06F9/34 ,  G06F3/06 ,  G06F11/07 ,  G06F9/38

Abstract: Techniques and mechanisms for circuitry of a processor to automatically provide, and perform an operation based on, metadata indicating an uninitialized memory block. In an embodiment, processor circuitry detects a software instruction which specifies a first operation to be performed based on some data at a memory block. Metadata corresponding to said data comprises an identifier of whether the data is based on an uninitialized memory condition. Processing of the instruction, includes the processor circuitry automatically performing a second operation based on the identifier. The second operation is performed independent of any instruction of the application which specifies the second operation. In another embodiment, execution of the instruction (if any) is conditional upon an evaluation which is based on the state identifier, or the second operation is automatically performed based on an execution of the first instruction.

公开(公告)号：US20200319886A1

公开(公告)日：2020-10-08

申请号：US16799619

申请日：2020-02-24

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Joseph Nuzman ,  Jonas Svennebring ,  Doddaballapur N. Jayasimha ,  Samantika S. Sury ,  David A. Koufaty ,  Niall D. McDonnell ,  Yen-Cheng Liu ,  Stephen R. Van Doren ,  Stephen J. Robinson

IPC: G06F9/30 ,  G06F12/0875

Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations. In one example, a system includes an RAO instruction queue stored in a memory and having entries grouped by destination cache line, each entry to enqueue an RAO instruction including an opcode, a destination identifier, and source data, optimization circuitry to receive an incoming RAO instruction, scan the RAO instruction queue to detect a matching enqueued RAO instruction identifying a same destination cache line as the incoming RAO instruction, the optimization circuitry further to, responsive to no matching enqueued RAO instruction being detected, enqueue the incoming RAO instruction; and, responsive to a matching enqueued RAO instruction being detected, determine whether the incoming and matching RAO instructions have a same opcode to non-overlapping cache line elements, and, if so, spatially combine the incoming and matching RAO instructions by enqueuing both RAO instructions in a same group of cache line queue entries at different offsets.

公开(公告)号：US20190235948A1

公开(公告)日：2019-08-01

申请号：US16224579

申请日：2018-12-18

Applicant: Intel Corporation

Inventor： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

IPC: G06F11/07 ,  G06F12/109 ,  G06F9/38 ,  G06F12/00

CPC classification number: G06F11/0751 ,  G06F9/38 ,  G06F11/073 ,  G06F12/00 ,  G06F12/109 ,  G06F12/145 ,  G06F21/60 ,  G06F2212/1032 ,  G06F2212/1052 ,  G06F2212/656

Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

公开(公告)号：US10133669B2

公开(公告)日：2018-11-20

申请号：US15352272

申请日：2016-11-15

Applicant: INTEL CORPORATION

Inventor： Pavel I. Kryukov ,  Stanislav Shwartsman ,  Joseph Nuzman ,  Alexandr Titov

IPC: G06F12/08 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0837 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891

Abstract: An example system on a chip (SoC) includes a cache, a processor, and a predictor circuit. The cache may store data. The processor may be coupled to the cache and store a first data set at a first location in the cache and receive a first request from an application to write a second data set to the cache. The predictor circuit may be coupled to the processor and determine that a second location where the second data set is to be written to in the cache is nonconsecutive to the first location, where the processor is to perform a request-for-ownership (RFO) operation for the second data set and write the second data set to the cache.