公开(公告)号：US10261879B2

公开(公告)日：2019-04-16

申请号：US14757919

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Bret L. Toll ,  Konrad K. Lai ,  Matthew C. Merten ,  Martin G. Dixon

IPC: G06F15/00 ,  G06F9/00 ,  G06F9/44 ,  G06F7/00 ,  G06F11/28 ,  G06F9/46 ,  G06F9/30 ,  G06F12/0811 ,  G06F9/38 ,  G11C7/10 ,  G06F11/22 ,  G06F11/263 ,  G06F12/0897 ,  G06F12/0817 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F11/14 ,  G06F11/25

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

公开(公告)号：US10261792B2

公开(公告)日：2019-04-16

申请号：US15408632

申请日：2017-01-18

Applicant: Intel Corporation

Inventor： Michael W. Chynoweth ,  Peggy J. Irelan ,  Matthew C. Merten ,  Seung-Woo Kim ,  Laura A. Knauth ,  Stanislav Bratanov

IPC: G06F9/30 ,  G06F11/34 ,  G06F12/0875

Abstract: In one embodiment, a processor includes a performance monitor including a last branch record (LBR) stack to store a call stack to an event of interest, where the call stack is collected responsive to a trigger for the event. The processor further includes logic to control the LBR stack to operate in a call stack mode such that an entry to a call instruction for a leaf function is cleared on return from the leaf function. Other embodiments are described and claimed.

公开(公告)号：US09904553B2

公开(公告)日：2018-02-27

申请号：US15159040

申请日：2016-05-19

Applicant: Intel Corporation

Inventor： Bambang Sutanto ,  Srikanth T. Srinivasan ,  Matthew C. Merten ,  Chia Yin Kevin Lai ,  Ammon J Christiansen ,  Justin M. Deinlein

IPC: G06F9/38 ,  G06F9/48

CPC classification number: G06F9/384 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/4881

Abstract: A processor and method are described for scheduling operations for execution within a reservation station. For example, a method in accordance with one embodiment of the invention includes the operations of: classifying a plurality of operations based on the execution ports usable to execute those operations; allocating the plurality of operations into groups within a reservation station based on the classification, wherein each group is serviced by one or more execution ports corresponding to the classification, and wherein two or more entries within a group share a common read port and a common write port; dynamically scheduling two or more operations in a group for concurrent execution based on the ports capable of executing those operations and a relative age of the operations.

公开(公告)号：US09733939B2

公开(公告)日：2017-08-15

申请号：US13631664

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： Vijaykumar Balaram Kadgi ,  James D. Hadley ,  Avinash Sodani ,  Matthew C. Merten ,  Morris Marden ,  Joseph A. McMahon ,  Grace C. Lee ,  Laura A. Knauth ,  Robert S. Chappell ,  Fariborz Tabesh

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30105 ,  G06F9/384

Abstract: A processor includes a processing unit including a storage module having stored thereon a physical reference list for storing identifications of physical registers that have been referenced by multiple logical registers, and a reclamation module for reclaiming physical registers to a free list based on a count of each of the physical registers on the physical reference list.

公开(公告)号：US09612938B2

公开(公告)日：2017-04-04

申请号：US13895595

申请日：2013-05-16

Applicant: Intel Corporation

Inventor： Frank Binns ,  Matthew C. Merten ,  Mayank Bomb ,  Beeman C. Strong ,  Peter Lachner ,  Jason W. Brandt ,  Itamar Kazachinsky ,  Ofer Levy ,  Md A. Rahman

IPC: G06F7/38 ,  G06F3/00 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F11/3636 ,  G06F11/3024 ,  G06F11/3055 ,  G06F11/3476 ,  G06F11/348 ,  G06F2201/865

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for providing status of a processing device with a periodic synchronization point in an instruction tracing system. For example, the method may include generating a boundary packet based on a unique byte pattern in a packet log. The boundary packet provides a starting point for packet decode. The method may also include generating a plurality of state packets based on status information of the processor. The plurality of state packets follows the boundary packet when outputted into the packet log.

公开(公告)号：US09606602B2

公开(公告)日：2017-03-28

申请号：US14318999

申请日：2014-06-30

Applicant: Intel Corporation

Inventor： Anupama Suryanarayanan ,  Matthew C. Merten ,  Ryan L. Carlson

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F9/3824 ,  G06F9/3836

Abstract: In an embodiment, a processor includes at least one core including a first core. The first core includes memory execution logic to execute one or more memory instructions, memory dispatch logic to output a plurality of memory instructions to the memory execution logic, and reactive memory instruction tracking logic. The reactive memory instruction tracking logic is to detect an onset of a memory instruction high power event associated with execution of at least one of the memory instructions, and to indicate to the memory dispatch logic to throttle output of the memory instructions to the memory execution logic responsive to detection of the onset of the memory instruction high power event. The processor also includes cache memory coupled to the at least one core. Other embodiments are described and claimed.

公开(公告)号：US09465680B1

公开(公告)日：2016-10-11

申请号：US14721819

申请日：2015-05-26

Applicant: INTEL CORPORATION

Inventor： Michael W. Chynoweth ,  Jonathan D. Combs ,  Angela D. Schmid ,  Kimberly C. Weier ,  Ahmad Yasin ,  Jason W. Brandt ,  Charlie J. Hewett ,  Seth Abraham ,  Matthew C. Merten

IPC: G06F13/00 ,  G06F9/54 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F9/542 ,  G06F11/00 ,  G06F11/3024 ,  G06F11/3409

Abstract: A processor and method are described for implementing performance monitoring using a fixed function performance counter. For example, one embodiment of an apparatus comprises: a fixed function performance counter to decrement or increment upon occurrence of an event in the processing device; a precise event based sampling (PEBS) enable control communicably coupled to the fixed function performance counter; a PEBS handler to generate and store a PEBS record comprising architectural metadata defining a state of the processing device at a time of generation of the PEBS record; and a non-precise event based sampling (NPEBS) module communicably coupled to the PEBS enable control and the PEBS handler, the NPEBS module to cause the PEBS handler to generate the PEBS record for the event upon the fixed function performance counter reaching a specified value.

Abstract translation: 描述了使用固定功能性能计数器实现性能监视的处理器和方法。 例如，设备的一个实施例包括：固定功能性能计数器，用于在处理设备中发生事件时递减或递增; 精确的基于事件的采样（PEBS）使能控制可通信地耦合到固定功能性能计数器; PEBS处理器，用于生成和存储PEBS记录，其包括在生成PEBS记录时定义处理设备的状态的架构元数据; 以及可通信地耦合到PEBS使能控制和PEBS处理器的非精确事件采样（NPEBS）模块，NPEBS模块使固定功能性能计数器达到指定值时使PEBS处理程序生成事件的PEBS记录 。

公开(公告)号：US09372698B2

公开(公告)日：2016-06-21

申请号：US13931864

申请日：2013-06-29

Applicant: INTEL CORPORATION

Inventor： Bambang Sutanto ,  Srikanth T. Srinivasan ,  Matthew C. Merten ,  Chia Yin Kevin Lai ,  Ammon J Christiansen ,  Justin M Deinlein

IPC: G06F9/38 ,  G06F9/48

CPC classification number: G06F9/384 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/4881

Abstract: A processor and method are described for scheduling operations for execution within a reservation station. For example, a method in accordance with one embodiment of the invention includes the operations of: classifying a plurality of operations based on the execution ports usable to execute those operations; allocating the plurality of operations into groups within a reservation station based on the classification, wherein each group is serviced by one or more execution ports corresponding to the classification, and wherein two or more entries within a group share a common read port and a common write port; dynamically scheduling two or more operations in a group for concurrent execution based on the ports capable of executing those operations and a relative age of the operations.

Abstract translation: 描述了用于在保留站内执行的调度操作的处理器和方法。 例如，根据本发明的一个实施例的方法包括以下操作：基于可用于执行这些操作的执行端口对多个操作进行分类; 基于分类，将多个操作分配到保留站内的组中，其中每个组由对应于分类的一个或多个执行端口服务，并且其中组内的两个或多个条目共享公共读取端口和公共写入 港口; 基于能够执行这些操作的端口和操作的相对年龄，动态地调度用于并发执行的组中的两个或更多个操作。

公开(公告)号：US10223227B2

公开(公告)日：2019-03-05

申请号：US14998052

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Bret L. Toll ,  Konrad K. Lai ,  Matthew C. Merten ,  Martin G. Dixon

IPC: G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F11/28 ,  G06F9/46 ,  G06F9/30 ,  G06F12/0811 ,  G06F9/38 ,  G11C7/10 ,  G06F11/22 ,  G06F11/263 ,  G06F12/0897 ,  G06F12/0817 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F11/14 ,  G06F11/25

Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.

公开(公告)号：US10216616B2

公开(公告)日：2019-02-26

申请号：US15201405

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Beeman C. Strong ,  Matthew C. Merten ,  Lee W. Baugh

IPC: G06F11/36 ,  G06F9/30 ,  G06F12/0875 ,  G06F9/38 ,  G06F11/34

Abstract: A processor is disclosed and comprises a front end including circuitry to decode instructions from an instruction stream; a data cache unit including circuitry to cache data for the processor; and a core triggering block (CTB) to provide integration between two or more different debug capabilities.