公开(公告)号：US11132319B2

公开(公告)日：2021-09-28

申请号：US15870679

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Christopher Wing Hong Ngau ,  Hooi Kar Loo ,  Poh Thiam Teoh ,  Shashitheren Kerisnan ,  Maxim Dan ,  Chee Siang Chow

IPC: G06F1/3234 ,  G06F13/38 ,  G06F13/40 ,  H04B10/27 ,  G06F13/42

Abstract: Aspects of the embodiments are directed to systems, methods, and devices for controlling power management entry. A PCIe root port controller can be configured to receive, at a downstream port of the root port controller, from an upstream switch port, a first power management entry request; reject the first power management entry request; transmit a negative acknowledgement message to the upstream switch port; initiate a timer for at least 20 microseconds; during the 20 microseconds, ignore any power management entry requests received from the upstream switch port; receive, after the expiration of the 20 microseconds, a subsequent power management entry request; accept the subsequent power management entry request; and transmit an acknowledgement of the acceptance of the subsequent power management entry request to the upstream switch port.

公开(公告)号：US09563256B2

公开(公告)日：2017-02-07

申请号：US13734577

申请日：2013-01-04

Applicant: Intel Corporation

Inventor： Sun Zheng E ,  Ting Lok Song ,  Poh Thiam Teoh ,  Jennifer Chin ,  Say Cheong Gan ,  Sujea Lim ,  Su Wei Lim

IPC: G06F1/32

CPC classification number: G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

Abstract: Particular embodiments described herein can offer a method that includes powering down a root port; initiating a first downstream cycle by a central processing unit (CPU) to the root port; identifying a power up activity for the CPU; and triggering an exit flow for a power state in conjunction with sending a second downstream cycle to the root port. In more particular embodiments, the triggering of the exit flow for the power state and the sending of the second downstream cycle to the root port occurs in a substantially parallel fashion. In addition, a prewake indicator can be sent to the root port to trigger the exit flow before the CPU is powered up and the second downstream cycle is sent.

Abstract translation: 本文描述的特定实施例可以提供一种方法，其包括断电根端口; 通过中央处理单元（CPU）向根端口发起第一下游循环; 识别CPU的加电活动; 并且触发用于电力状态的退出流，同时向根端口发送第二下游循环。 在更具体的实施例中，用于功率状态的出口流的触发和将第二下游循环发送到根端口以基本上平行的方式发生。 另外，在CPU上电并发送第二个下游周期之前，可以将根据端口发送预取指示符以触发退出流。

公开(公告)号：US20240106644A1

公开(公告)日：2024-03-28

申请号：US17954157

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Aditya Katragada ,  Geoffrey Strongin ,  Prakash Iyer ,  Rajesh Banginwar ,  Poh Thiam Teoh ,  Gary Wallichs

IPC: H04L9/08

CPC classification number: H04L9/0891 ,  H04L9/0894

Abstract: A system and method of enhancing the mitigation of side channel attacks on platform interconnects using endpoint HW based detection, synchronization, and re-keying include generating a set of keys for link encryption based on a high entropy seed, storing the set of keys in a deterministic order in a register, detecting that a re-key programmable threshold is met during link encryption with a device, identifying a synchronization point associated with the device, where the synchronization point indicates the device is ready to switch a current key used for link encryption, and synchronizing a rekeying event with the device.

公开(公告)号：US20180098320A1

公开(公告)日：2018-04-05

申请号：US15282411

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Say Cheong Gan ,  Poh Thiam Teoh ,  Kar HK Loo ,  Sun Zheng E ,  Keng Dar Ang

IPC: H04W72/04 ,  H04L5/00 ,  H04L12/26

CPC classification number: H04W72/0446 ,  H04J3/0664 ,  H04L5/0055 ,  H04L43/106

Abstract: Aspects of the embodiments are directed to systems, methods, and devices, such as an upstream device that includes an input/output port. The input/output port configured to receive a message from an output port of a downstream device; transmit a plurality of acknowledgement messages to the downstream device; and transmit a response message to the received message to the downstream device.

公开(公告)号：US09513662B2

公开(公告)日：2016-12-06

申请号：US13734612

申请日：2013-01-04

Applicant: Intel Corporation

Inventor： Jennifer Chin ,  Su Wei Lim ,  Poh Thiam Teoh ,  Ting Lok Song ,  Sun Zheng E ,  Say Cheong Gan ,  Sujea Lim ,  Ming Yi Lim

IPC: G06F1/00 ,  G06F1/16 ,  G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/1626 ,  G06F1/3206 ,  G06F1/3218 ,  G06F1/3243 ,  G06F13/4282 ,  G06F2213/0026 ,  Y02D10/151 ,  Y02D10/152

Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.

Abstract translation: 本文描述的特定实施例可以提供一种用于管理至少一个处理器的功率的方法，该处理器包括评估与电子设备相关联的多个端口; 确定与所述端口中的至少一个相关联的特定引脚没有接收到信号; 禁用与所述电子设备相关联的静噪功能; 以及与电子设备的物理层（PHY）相关联的门控功率。